The massive amounts of monitoring data in network applications bring an urgent need for intelligent operation in large distributed systems. The key problem is precisely detecting anomalies in multivariate time series (MTS) monitoring metrics with the awareness of different application scenarios. Unsupervised MTS anomaly detection methods aim at detecting data anomalies from historical MTS without considering the out-of-band information (including user feedback and background information like code deployment status), which leads to poor performance in practice. To take advantage of the out-of-band information, we propose ACVAE, an MTS anomaly detection algorithm through active learning and contrast VAE-based detection models, which simultaneously learns MTS data’s normal and anomalous patterns for anomaly detection. We also use a learnable prior to capture system status from the background information. Moreover, we propose a query model for VAE-based methods, which can learn to query labels of the most useful instances to train the detection model. We evaluate our algorithm on three different monitoring situations in eBay’s search back-end systems.ACVAEachieves a range F1 score of 0.68~0.96 with only 3% labels, significantly outperforming the best competing methods by 0.18~0.50, and even better than a supervised ensemble method designed by domain experts in eBay.

Web search engines are now using tens of thousands of index servers that consume huge amount of power. In this paper, we investigate FPGAs as the implementation platform for power efficient index serving. We propose the architecture of an FPGA-based inverted index search engine, as well as implementations of essential components, including decoder, matcher and ranker. We successfully boot up the FPGA-based search engine and run experiments on real-world data from a commercial search engine. The targeted FPGA-based hardware index server could achieve up to 19.52X power efficiency and 7.17X price efficiency over an Intel Xeon server with highly optimized software. This is the first complete work using FPGAs to implement query processing for Web search engines.

Ultrasound Imaging is one of the most widely used medical imaging methods, and beamforming is the enabling technology of ultrasound imaging, which directly influences the image quality. The critical problem of modern ultrasound imaging system is generating high resolution images at high frame rate. To solve this problem, real-time high precision beamforming delay parameters must be generated. This paper presents the design and implementation of a pipelined high precision beamforming delay calculator for ultrasound imaging, which uses 10-stage pipelined CORDIC (Coordinate Rotation Digital Computer) processor to perform fully pipelined architecture. The presented delay calculator calculates delay parameters with high precision, which can greatly improve the image quality. And fully pipelined architecture can also provide high frame rate. The design has been synthesized for an Altera Arria-II GX FPGA with speed grade 4. A delay calculator requires about 3,238 out of 50,600 available ALUTs (6.4%), and a 64-channel dual-beam system needs 24 such delay calculator modules. The delay calculators run in parallel, and one of them can generate 300 million delay parameters per second.