Quantum computing is a compelling new technology that is becoming increasingly practical as time progresses. Quantum computers have the potential to solve problems of great complexity and magnitude across many different industries, utilizing appropriate quantum algorithms. Given the evolving stage of quantum computing, characterized by a limited number of operational quantum computers that demand extensive cooling, face decoherence issues, and incur significant fabrication costs, there exists a pronounced need for quantum computer simulators. In this work, a reconfigurable closed-loop CBRAM crossbar system has been developed for the execution and acceleration of quantum algorithm simulation, leveraging analog in-memory computing. The circuit supports a universal set of quantum gates representation, and through its reprogramming capabilities and feedback loop, can compute any quantum algorithm. To demonstrate its functionality, the 3-qubit Grover algorithm is executed on the proposed circuit. Building on the extensive circuit simulation, a comparative analysis of power and speed between the proposed nanoelectronic circuit and conventional hardware has been conducted, demonstrating the high efficiency and performance gains, followed by a scalability analysis. Furthermore, a framework has been developed that supports the design of custom closed-loop memristive crossbars through a graphical user interface (GUI), providing the user with the capability to execute quantum algorithms and examine the programming and computations of the circuit, assisting with the realization of a hardware prototype.

This paper presents the applicability of a mycelium-inspired reservoir network through an innovative extension of the Memristive Oscillating Cellular Automata (MOCA) circuit-based network. Drawing on the adaptive, self-organizing properties of mycelium, this MOCA grid employs SiNx-based RRAMs to form reconfigurable, dynamic connections that replicate mycelial network behaviors. Using the Stanford-PKU RRAM model, the non-linear properties of the fabricated devices have been characterized, establishing a flexible reservoir network capable of transforming and encoding input signals. The network has been evaluated, demonstrating small-world characteristics, including high clustering and short average path lengths, critical for effective information propagation and complex local dynamics. The resulting adaptable circuit offers a scalable foundation for future applications in bioinspired reservoir computing.

The memristor crossbar architecture is a new technology that combines memory and computing on the same chip, finding numerous applications in modern bio-inspired computing systems. Recently, memristor-coupled Chua Circuit Networks (MCCNs) have been developed for the experimental confirmation of collective nonlinear phenomena, such as chimera states, that are also observed in the brain. For highly dense topologies, however, memristor crossbars can be prone to certain vulnerabilities. In this paper, we investigate the impact of sneak-path currents (SPCs) on the collective behaviors of chaotic oscillator networks, uncovering the network's tolerance to various realistic memristor crossbar designs. Despite the fact that these states alter the synchronization regime map, our findings suggest that SPCs have no detrimental impact on the formation and stability of single or multiple chimera states. This coupling issue along with other possible challenges are thoroughly discussed with a focus on nonlinear dynamics, highlighting the reliability of memristor crossbars as a coupling mechanism for studying chimera states.

The analysis of noise signals produced by semiconductor devices provides significant information for the origin and the physical mechanisms causing them, allowing for the mitigation of the noise sources, and improving the device performance. Furthermore, noise signals generated by RRAM and memristive devices can be utilized in cryptography security for applications due to their stochastic nature, revealing the positive effects of noise signals. In this work, the noise signals originated from metal-nitride-semiconductor memristive devices are investigated in terms of the influence of the wafer substrate used to fabricate them. Specifically, metal-insulator-semiconductor memristive devices on bulk Si and Silicon-On-Insulator substrates are examined. Parameter extraction and statistical analyses are performed assuming the typical models used for MOSFET devices. Preliminary results suggest that the measured noise signals originated from electron traps sited in the silicon nitride resistance switching layer. However, devices on SOI substrate generate lower noise signals compared to bulk devices, probably due to the better isolation of the active layer.

There is a growing interest in quantum computers and quantum algorithm development. It has been proved that ideal quantum computers, with zero error rates and large decoherence times, can solve problems that are intractable for today’s classical computers. Quantum computers use two resources, superposition and entanglement, that have no classical analog. Since quantum computer platforms that are currently available comprise only a few dozen of qubits, the use of quantum simulators is essential in developing and testing new quantum algorithms. We present a novel quantum simulator based on memristor crossbar circuits and use them to simulate well-known quantum algorithms, namely the Deutsch and Grover quantum algorithms. In quantum computing the dominant algebraic operations are matrix-vector multiplications. The execution time grows exponentially with the simulated number of qubits, causing an exponential slowdown in quantum algorithm execution using classical computers. In this work, we show that the inherent characteristics of memristor arrays can be used to overcome this problem and that memristor arrays can be used not only as independent quantum simulators but also as a part of a quantum computer stack where classical computers accelerators are connected. Our memristive crossbar circuits are re-configurable and can be programmed to simulate any quantum algorithm.

Synchronization transition in neuromorphic networks has attracted much attention recently as a fundamental property of biological neural networks, which relies on network connectivity along with different synaptic features. In this work, an area-optimized FPGA implementation of an Asynchronous Cellular Automata Neuron model that exhibits discrete-state neuron dynamics is introduced. The proposed neuron model is capable of reproducing various neuromorphic oscillations observed in biological neurons using less hardware resources than previous implementations. We investigate synchronization transitions with a focus on the emergence of chimera states in a ring-based network consisting of hardware-based neurons with electrical synaptic coupling. In particular, we study the effects on the network’s phase synchronization through changing two control parameters: the coupling range and the coupling strength. We indicate that via proper configuration of the coupling parameters, we influence the synchronization transition and reveal chimera states which have been associated with neurological disorders.

Over the last years there has been significant progress in the development of quantum computers. It has been demonstrated that they can accelerate the solution of various problems exponentially compared to today's classical computers, harnessing the properties of superposition and entanglement, two resources that have no classical analog. Since quantum computer platforms that are currently available comprise only a few tenths of qubits, as well as the access to a fabricated quantum computer is time limited for the majority of researchers, the use of quantum simulators is essential in developing and testing new quantum algorithms. Taking inspiration from previous work on developing a novel quantum simulator based on memristor crossbar circuits, in this work, a framework that automates the circuit design of emulated quantum gates is presented. The proposed design framework deals with the generation and programming of memristor crossbar configuration that incorporates the desirable quantum circuit, leading to a technology agnostic design tool. To such a degree, various quantum gates can be efficiently emulated on memristor crossbar configurations for various types of memristive devices, aiming to assist and accelerate the fabrication process of a memristor based quantum simulator.

The time series of the brain are usually characterized by the co-existence of synchronized and desynchronized behaviors. This kind of behavior is related to normal and disorderly functions of the brain. One of the suggested mechanisms to understand thoroughly this behavior are chimera states, which are characterized by the coincidence of coherent and incoherent dynamics that can be exploited through networks of symmetrically coupled identical oscillators. In this work, ring-based networks of Chua's circuits, the simplest electronic oscillators that perform chaotic and well-known bifurcation phenomena, have been extensively studied in memristive crossbars (Xbar), revealing various collective spatio-temporal behaviors, such as chimera states. With respect to different Xbar connectivities and via SPICE-level circuit simulations, the proposed Xbar system proves its efficacy to reproduce spatio-temporal patterns spanning from complete synchronization and chimera states up to fully chaotic states.

Research progress in edge computing hardware, capable of demanding in-the-field processing tasks with simultaneous memory and low power properties, is leading the way towards a revolution in IoT hardware technology. Resistive random access memories (RRAM) are promising candidates for replacing current non-volatile memories and realize storage class memories, but also due to their memristive nature they are the perfect candidates for in-memory computing architectures. In this context, a CMOS compatible silicon nitride (SiN) device with memristive properties is presented accompanied by a data-fitted model extracted through analysis of measured resistance switching dynamics. Additionally, a new phototransistor-based image sensor architecture with integrated SiN memristor (1P1R) was presented. The in-memory computing capabilities of the 1P1R device were evaluated through SPICE-level circuit simulation with the previous presented device model. Finally, the fabrication aspects of the sensor are discussed.