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Steve G. Steinberg

dblp:00/1916 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1995
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Performance modeling and evaluation · 77% Processor architecture and microarchitecture · 23%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Compilers and program optimization
parallel language compilation
0.011995
Empirical Evaluation of the CRAY-T3D: A Compiler Perspective · ISCA 1995
Performance modeling and evaluation › benchmarking
microbenchmarking
0.011995
Empirical Evaluation of the CRAY-T3D: A Compiler Perspective · ISCA 1995

Methods — techniques the papers use, named apart from their topics

microbenchmarking · 0.0
YearPublicationVenuePosition
1995 Empirical Evaluation of the CRAY-T3D: A Compiler Perspective
abstract
Most recent MPP systems employ a fast microprocessor surrounded by a shell of communication and synchronization logic. The CRAY-T3D provides an elaborate shell to support global-memory access, prefetch, atomic operations, barriers, and block transfers. We provide a detailed empirical performance characterization of these primitives using micro-benchmarks and evaluate their utility in compiling for a parallel language. We have found that the raw performance of the machine is quite impressive and the most effective forms of communication are prefetch and write. Other shell provisions, such as the bulk transfer engine and the external Annex register set, are cumbersome and of little use. By evaluating the system in the context of a language implementation, we shed light on important trade-offs and pitfalls in the machine architecture.
Remzi H. Arpaci-Dusseau, David E. Culler, Arvind Krishnamurthy, Steve G. Steinberg, Katherine A. Yelick
ISCA4