The demand for cheaper, faster and more integrated semiconductor products is expected to drive the scaling of silicon technology, enabling continuance of Moore's law at least for another decade. However, technology scaling presents several manufacturing and design technology challenges that must be overcome to build semiconductor products in a cost effective manner. While some of the existing challenges that we face today such as power, process variations are expected to become worse at smaller geometries requiring innovations, new problems may arise in integrating heterogeneous technologies such as RF, MEMS on the same die/package. A myriad of design technology challenges starting from functional validation to timing validation and design for test to manufacturability must be addressed to successfully build products. The paper will highlight challenges and identify some of the opportunities in driving design technologies forward.

Current design tools are lagging behind and, in some cases, slowing the growth of the VLSI market. Disruptive design methods are necessary to bridge the gap. Abstraction and re-use are believed to be the most promising approaches. However, difficult open questions still exist in this new flow. In particular, how a high-level design can be transformed into an implementation while ensuring full (formal) verification of the correspondence between the models.

If EDA technology innovation drives return on investment, what drives innovation? Is it tied to the semiconductor retooling cycle? To productivity requirements? To Moores Law? Or is there something more fundamental that we are missing? What driving forces could result in a $30 billion EDA industry, and what role will innovation play? Will the industry provide the needed breakthroughs for their customers, or seek instead the lowest common denominator user? Will designers “roll their own” tools or seek common solutions? How does EDA innovation track with the semiconductor business cycle? Does a slowdown accelerate or depress creation of new tools and new designs? Panelists will discuss the forces at work in the EDA industry of tomorrow.

As microprocessor design progresses from tens of millions of transistors on a chip using 0.18-/spl mu/m process technology to approximately a billion transistors on a chip using 0.10-/spl mu/m and finer process technologies, the microprocessor designer faces unprecedented Electronic Design Automation (EDA) challenges over the future generations of microprocessors. This paper describes the changes in the design environment that will be necessary to develop increasingly complex microprocessors. In particular, the paper describes the current status and the future challenges along three important areas in a design flow: design correctness, performance verification and power management.