Quantum electronic devices such as resonant tunneling diodes and transistors are now beginning to be used in ultrafast and compact circuit designs. These devices exhibit negative differential resistance (NDR) and/or negative transconductance in their I-V characteristics and have active dimensions of a few nanometers. Since the conventional drift-diffusion approximation is not valid for simulation of device behavior at this microscopic scale, quantum simulation models based on the Schrodinger equation are required to accurately predict the behavior of the device. However, these models are too slow for circuit simulation. This paper describes a modeling scheme that maintains the accuracy of the quantum simulation while achieving satisfactory speed for circuit simulation, and is applicable to a wide range of two and three terminal resonant tunneling devices and may also be extended to future scaled-down MOS and bipolar devices. A self-consistent solution of the Poisson and the Schrodinger equations for various bias points is used to build up tables of conductances, capacitances and other parameters. Table-lookup methods are then used during circuit simulation. Convergence techniques have been developed to overcome the problems caused by the NDR characteristics and the lookup-table model in simulation. While implementation details are presented for a resonant tunneling transistor (RTT), models for several other quantum electronic devices have also been implemented in NDR-SPICE.>

The authors point out that a typical computer-aided design environment consists of a number of workstations connected together by a high-speed local area network. A placement program that makes use of this distributed computing environment to achieve linear speedup without sacrificing the quality of the results obtained by the serial version of the program is presented. The placement program is based on the genetic algorithm, which is a heuristic search method inspired by biological evolution models. The parallel implementation has other desirable features such as the ability to operate in a heterogeneous network environment and dynamic and static load balancing. The implementation of the placement program and detailed experimental studies of the behavior of the algorithm with various parameter settings, network capabilities, and communication patterns are described.>

Gallium arsenide memories, which are now beginning to be used commercially, are subject to certain unusual parametric faults, not normally seen in silicon or other memory devices. This paper studies the behavior of gallium arsenide high electron mobility transistor (HEMT) memories in the presence of material defects, processing errors and design errors to formulate efficient testing schemes. All defects and errors are mapped into equivalent circuit modifications and the resulting circuits are analyzed and simulated to observe the fault effects. Certain complex pattern-sensitive faults described in the testing literature are not observed at all, while certain other faults which have not been previously studied, are observed. It is shown that by slightly modifying and reordering existing test procedures, all faults in these RAMs can be tested.>

Gallium Arsenide memories, which are now beginning to be used commercially, are subject to certain unusual parametric faults, not normally seen in silicon or other memory devices. This paper analyzes the causes of these parametric faults by first mapping the observed errors in the fabrication process to circuit behavior; these modified circuits are then shown to cause new types of pattern-sensitive faults and data retention problems. It is shown that by slightly modifying and reordering existing test procedures, all faults in these RAM’s can be adequately tesled.