We propose a new group of slotted ring protocols called REALNET. In REALNET networks the ring access scheme, traffic control and management, and slot allocation for voice and data cycles are made highly adaptive. We analyze, simulate and compare different REALNET networks which use different methods for their cycle alternation strategy. The results show that REALNET networks that use prediction satisfy strict voice delay requirements, allow small percentages of voice packet loss for a large number of active voice stations, as well as providing higher bandwidth utilization, and giving lower delays and higher throughputs for data packets when compared to other integrated services protocols.>

The procedures introduced in this paper convert redundant circuits into irredundant circuits for testing purposes. In a redundant circuit, there are redundant connections which contribute no unique l's or 0's to the output of the circuit. These redundant connections are contained in the circuit for specific purposes, such as hazard protection, integrated circuit standardization, structural purposes, correct operation in the presence of faults, and other reasons. Most faults on these redundant connections cannot be detected due to the unchanging output. An irredundant circuit contains no redundant connections and all lines are completely testable.

This paper describes the application of generalized computer-assisted modeling techniques to support data communication engineering instruction. The characteristics of multidrop line networks are identified and performance investigated with IBM's GPSS V Simulation Language. Network connectivity is illustrated with a Fortran language program.

This paper describes an algorithm for minimizing an arbitrary Boolean function. The approach differs from most previous procedures in which first all prime implicants are found and then a minimal set is then determined. This procedure imposes a set of conditions on the selection of the next prime implicant in order to obtain a near minimal sum-of-products realization. Extension to the multiple output and incompletely specified function cases is given. An important characteristic of the proposed procedure is the relatively small amount of computer time spent to solve a problem, as compared to other procedures. The MINI algorithm may give better results for a large number of inputs and outputs if relatively few product terms are needed. This procedure is also well suited to find a solution for programmable logic arrays (PLA's) which internally implement large Boolean functions as a sum-of-products.

Mealy synchronous machines cannot be implemented by Chuang and Das"1 procedure for multiple-input change asynchronous circuits. The circuit must be changed to handle this common type of machine.

Bosson and Hong1 have developed an effective procedure for multiple fault detection. However, their claim that their procedure gives near-minimal results is not necessarily the case.

Recently, a good deal of research has been conducted on the use of transition-or edge-sensitive elements in the design of asynchronous sequential circuits. Transition-sensitive memory elements have been used extensively in the implementation of synchronous sequential circuits as a means of eliminating the restrictions placed on pulsewidth. Several means are available for achieving multiple-input or universal transition-sensitive flip-flops. Here the approach is to employ a basic flip-flop as the memory element and add transition-sensitive gating to the flip-flop input. In this manner, any type of transition-sensitive flip-flop may be configured.

A circuit for generating a clock pulse for asynchronous circuits is given, and when used with transition sensitive flip-flops eliminates critical races for an arbitrary state assignment. Thus the minimum number of internal variables may be used. Furthermore, logic and sequential hazards will not affect the circuit performance.

This correspondence shows that the Necula [1] and Slagle, Chang. and Lee [2] methods for determining prime implicants are a mechanization of a method first given by Nelson [3], i. e., generating of all prime implicants by direct expansion of a conjunctive form to a disjunctive form.

Certain partitions in Tracey's assignment method may be eliminated because of impossible transitions on the inputs. This may reduce the complexity of the sequential machine.

It is shown that directed graphs can be used to generate a class of moderately efficient error-correcting codes, which are easily decodable.

A study of the efficiency, error-correcting capabilities, and limitations of graph theoretic block codes is presented. Augmentation of graph theoretic codes and their generation is discussed. It is shown that such augmentation techniques can substantially increase the level of efficiency of these codes and potentially could increase it to the level of the best available codes. Furthermore, the augmented graph theoretic codes are shown to be easily decodable.