The growing complexity and scale of Internet of Things (IoT) ecosystems have intensified the emergence of cyber threats and amplified the impact of data heterogeneity across devices. These environments are characterised by their inherent hostility, comprising resource-limited and intermittently connected devices. Consequently, this poses a considerable challenge to the stability and reliability of conventional Federated Learning (FL) approaches. Standard aggregation schemes such as FedAvg, FedProx, FedAdam, and SCAFFOLD often fail under such extreme non-Independent and Identically Distributed (non-IID) conditions, leading to unstable convergence and biased global models. This work introduces a double-clustering federated architecture for intrusion detection that coordinates training at two levels. Locally, lightweight micro-clustering organises client-side updates into consistent groups, reducing the influence of inconsistent local updates. At the server level, density-based (HDBSCAN) clustering discovers evolving families of distributionally compatible clients, allowing coordination to adapt as heterogeneity evolves over time. Clustering is stabilised across rounds through a stability-aware assignment rule. Training then proceeds via family-wise aggregation, producing one expert model per family and a global fallback model for outliers and unassigned participants. Extensive experiments on three public IoT cybersecurity datasets, X-IIoTID, RT-IoT22, and Edge-IIoTset, demonstrate the robustness of the proposed strategy across both lightweight and Deep Learning (DL) models. The architecture achieves up to 19.9% higher F1-score than standard FL methods and maintains over 90% of its peak performance even under severe non-IID conditions, while keeping runtime variations within ± 15%. These results establish clustering-guided coordination as a practical and resilient foundation for federated intrusion detection, capable of sustaining high accuracy and stability in the most adversarial IoT environments.

The rise of distributed architectures in Internet of Things (IoT) environments has significantly advanced both data processing and artificial intelligence. Notably, Multi-access Edge Computing (MEC) represents a distributed form of the Edge Computing paradigm, focussing on heterogeneous protocol management. In contrast, Federated Learning (FL) is an application-level framework designed to enable decentralised Machine Learning (ML) across devices without centralising data. Nevertheless, the combination of both technologies enables the creation of more efficient, scalable, and responsive systems. However, their integration into IoT brings substantial security challenges, including data poisoning, model manipulation, and the insertion of false nodes, all of which threaten the reliability of FL systems. Blockchain technology emerges as a promising solution to these challenges. It offers a decentralised, transparent, and immutable framework that ensures the authenticity and verification of data across the network. Through blockchain, node interactions are automated and secured, enhancing the integrity and trust in the learning process. This article proposes a blockchain-based architecture for FL within MEC-IoT systems, designed to mitigate security threats. The architecture emphasises data integrity, secure node interactions, and transparent audit trails while maintaining optimal model performance and accuracy, even under attack. It highlights the low resource consumption and minimal time overhead of blockchain integration, ensuring efficiency is not compromised. This integrated approach improves data security, supports secure collaborative learning, and fosters a more resilient and trustworthy IoT ecosystem.

The rapid expansion and growth of Internet of Things (IoT) and Industrial Internet of Things (IIoT) environments has led to an increase in the number of attacks and risks in these environments. This presents new cybersecurity challenges that require more advanced intrusion detection systems (IDS). However, IDS based on centralised Machine Learning (ML) face problems of scalability, latency, and privacy. In this context, Federated Learning (FL) offers a decentralised approach that allows multiple nodes to train models collaboratively without exposing sensitive data. This work presents a federated IDS tailored for IoT/IIoT environments and introduces FedWLA, an aggregation strategy that dynamically weights updates according to the quality and uncertainty of local data. The proposed architecture is evaluated through different IoT/IIoT traffic datasets orientated to cybersecurity and widely used in these environments. It shows comparable and even superior performance to centralised methods, with an average F1-Score ranging between 0.98 - 0.99 for the tests performed. Moreover, the proposed FedWLA strategy consistently outperforms other federated aggregation approaches, such as FedAvg and FedProx, particularly in heterogeneous scenarios. These results demonstrate the capability and potential of FL in intrusion detection, effectively leveraging the scalability and privacy advantages it offers.

In recent years we have seen the emergence of new industrial paradigms such as Industry 4.0/5.0 or the Industrial Internet of Things (IIoT). As the use of these new paradigms continues to grow, so do the number of threats and exploits that they face, which makes the IIoT a desirable target for cybercriminals . Furthermore, IIoT devices possess inherent limitations, primarily due to their limited resources. As a result, it is often impossible to detect attacks using solutions designed for other environments. Recently, Intrusion Detection Systems (IDS) based on Machine Learning (ML) have emerged as a solution that takes advantage of the large amount of data generated by IIoT devices to implement their functionality and achieve good performance , and the inclusion of the Multi-Access Edge Computing (MEC) paradigm in these environments provides the necessary computational resources to deploy IDS effectively. Furthermore, TabPFN has been considered as an attractive option for solving classification problems without the need to reprocess the data. However, TabPFN has certain drawbacks when it comes to the number of training samples and the maximum number of different classes that the model is capable of classifying. This makes TabPFN unsuitable for use when the dataset exceeds one of these limitations. In order to overcome such limitations, this paper presents a Weighted Fusion-Ensemble-based TabPFN (WFE-Tab) model to improve IDS performance in IIoT-MEC scenarios. The presented study employs a novel weighted fusion method to preprocess data into multiple subsets, generating different ensemble family TabPFN models. The resulting WFE-Tab model comprises four stages: data collection, data preprocessing , model training, and model evaluation. The performance of the WFE-Tab method is evaluated using key metrics such as Accuracy, Precision, Recall, and F1-Score, and validated using the Edge-IIoTset public dataset. The performance of the method is then compared with baseline and modern methods to evaluate its effectiveness, achieving an F1-Score performance of 99.81%.

Abstract The number of Internet of Things (IoT) forensic investigations has increased considerably over recent years due to the weak nature of the security measures of its devices. In order to ensure the effectiveness and completeness of their examinations, investigators rely on forensic models, frameworks and methodologies. However, given the novelty of the environment, the existing ones are not refined enough, and the conventional counterparts do not satisfy the requirements of the IoT. Consequently, further improvements are needed in order for a more suitable IoT methodology to be designed. After reviewing the proposals from the research community for the development of procedures for performing IoT investigations, this article presents a practical concept methodology for conducting IoT forensic investigations that details step by step the whole examination process from its opening to its closing. In order to test its effectiveness and feasibility, it is submitted to a theoretical, a practical and a hybrid evaluation. Firstly, by comparing its level of detail, practicality and content with the related work. Secondly, by assessing its performance in two practical scenarios that depict real-life forensic investigations and the challenges that they present. And, finally, by studying how the existing models from the research community would have behaved in these cases. After performing these three different evaluations, it can be concluded that the results achieved by the proposed methodology were satisfactory, confirmed the feasibility of the proposal and showed clear benefits compared with the related work in terms of practicality and level of detail.

Abstract The industrial internet of things (IIoT) has undergone rapid growth in recent years, which has resulted in an increase in the number of threats targeting both IIoT devices and their connecting technologies. However, deploying tools to counter these threats involves tackling inherent limitations, such as limited processing power, memory, and network bandwidth. As a result, traditional solutions, such as the ones used for desktop computers or servers, cannot be applied directly in the IIoT, and the development of new technologies is essential to overcome this issue. One approach that has shown potential for this new paradigm is the implementation of intrusion detection system (IDS) that rely on machine learning (ML) techniques. These IDSs can be deployed in the industrial control system or even at the edge layer of the IIoT topology. However, one of their drawbacks is that, depending on the factory’s specifications, it can be quite challenging to locate sufficient traffic data to train these models. In order to address this problem, this study introduces a novel IDS based on the TabPFN model, which can operate on small datasets of IIoT traffic and protocols, as not in general much traffic is generated in this environment. To assess its efficacy, it is compared against other ML algorithms, such as random forest, XGBoost, and LightGBM, by evaluating each method with different training set sizes and varying numbers of classes to classify. Overall, TabPFN produced the most promising outcomes, with a 10–20% differentiation in each metric. The best performance was observed when working with 1000 training set samples, obtaining an F1 score of 81% for 6-class classification and 72% for 10-class classification.

Abstract In recent years, the Internet of Things (IoT) has grown rapidly, as has the number of attacks against it. Certain limitations of the paradigm, such as reduced processing capacity and limited main and secondary memory, make it necessary to develop new methods for detecting attacks in real time as it is difficulty to adapt as has the techniques used in other paradigms. In this paper, we propose an architecture capable of generating complex event processing (CEP) rules for real-time attack detection in an automatic and completely unsupervised manner. To this end, CEP technology, which makes it possible to analyze and correlate a large amount of data in real time and can be deployed in IoT environments, is integrated with principal component analysis (PCA), Gaussian mixture models (GMM) and the Mahalanobis distance. This architecture has been tested in two different experiments that simulate real attack scenarios in an IoT network. The results show that the rules generated achieved an F1 score of .9890 in detecting six different IoT attacks in real time.

Internet of Things (IoT) devices and their firmware are notorious for their lifelong vulnerabilities. As device infection increases, vendors also fail to release patches at a competitive pace. Despite security in acrshort IoT being an active area of research, prior work has mainly focused on vulnerability detection and exploitation, threat modeling, and protocol security. However, these methods are ineffective in preventing attacks against legacy and End-Of-Life devices that are already vulnerable. Current research mainly focuses on implementing and demonstrating the potential of malicious modifications. Hardening emerges as an effective solution to provide acrshort IoT devices with an additional layer of defense. In this article, we bridge these gaps through the design of $\textit {HALE-IoT}$ , a generically applicable systematic approach to HArdening LEgacy acrshort IoT non-low-end devices by retrofitting defensive firmware modifications without access to the original source code. $\textit {HALE-IoT}$ approaches this nontrivial task via binary firmware reversing and modification while being underpinned by a semiautomated toolset that aims to keep cybersecurity of such devices in a hale state. Our focus is on both modern and, especially, legacy or obsolete acrshort IoT devices as they become increasingly prevalent. To evaluate the effectiveness and efficiency of HALE-IoT, we apply it to a wide range of acrshort IoT devices by retrofitting 395 firmware images with defensive implants containing an intrusion prevention system in the form of a Web Application Firewall (for prevention of Web-attack vectors), and an HTTPS-proxy (for latest and full end-to-end HTTPS support) using emulation. We also test our approach on four physical devices, where we show that HALE-IoT successfully runs on protected and quite constrained devices with as low as 32 MB of RAM and 8 MB of storage. Overall, in our evaluation, we achieve good performance and reliability with a remarkably accurate detection and prevention rate for attacks coming from both real CVEs and synthetic exploits.

Switched telephone networks are a key and ubiquitous infrastructure. Recent technological advances have integrated modern and inexpensive systems into these networks in order to use the Internet to place calls via Voice over IP (VoIP). The evolution of this technology has also led to an increase in the number and sophistication of the techniques used by criminals to commit fraud. Specifically, with the emergence of VoIP, attackers can now adapt tools commonly used by cybercriminals, such as botnets, to make their attacks more complex and insidious. For example, through bots they can dial multiple numbers automatically, enabling them to target a greater number of victims, and do so more quickly. While recent studies have shed light on how certain parts of this ecosystem work, it is still unclear how attacks on VoIP systems contribute to this type of fraud. This paper presents a novel VoIP honeypot that captures voice interactions, in addition to employing low-level telemetry. With the study of how attackers obtain access to our honeypot and the actions they perform, we present an overview of the most prevalent types of fraud used in this ecosystem, including unique insights into the origin of the attacks and the destination of calls made through our architecture. Finally, we analyze in depth the actions taken to study the different types of telephony fraud.

The Internet of Things (IoT) paradigm demands adapting traditional cybersecurity solutions to address the inherent limitations of IoT environments, in particular their low computational power and limited amount of memory and bandwidth. The Complex Event Processing (CEP) technology has proven to be useful in this context by deploying a CEP engine for detecting real-time attacks in an IoT network. However, CEP is only capable of detecting attacks that have been previously modeled as event patterns. This requires a domain expert who knows the conditions that must be satisfied so that certain attacks can be detected, thus identifying unmodeled ones is not possible. This paper aims to address this problem by proposing a machine learning algorithm that allows for the automatic creation of CEP patterns based on categorized data if the goal is to classify attacks, or even uncategorized data if the objective is to detect anomalies. An evaluation of the effectiveness of the automatically generated patterns for recognizing different attacks in IoT environments is also conducted in this paper.

The Internet of Things (IoT) is growing globally at a fast pace: people now find themselves surrounded by a variety of IoT devices such as smartphones and wearables in their everyday lives. Additionally, smart environments, such as smart healthcare systems, smart industries and smart cities, benefit from sensors and actuators interconnected through the IoT. However, the increase in IoT devices has brought with it the challenge of promptly detecting and combating the cybersecurity attacks and threats that target them, including malware, privacy breaches and denial of service attacks, among others. To tackle this challenge, this paper proposes an intelligent architecture that integrates Complex Event Processing (CEP) technology and the Machine Learning (ML) paradigm in order to detect different types of IoT security attacks in real time. In particular, such an architecture is capable of easily managing event patterns whose conditions depend on values obtained by ML algorithms. Additionally, a model-driven graphical tool for security attack pattern definition and automatic code generation is provided, hiding all the complexity derived from implementation details from domain experts. The proposed architecture has been applied in the case of a healthcare IoT network to validate its ability to detect attacks made by malicious devices. The results obtained demonstrate that this architecture satisfactorily fulfils its objectives.

Malware targeting interconnected infrastructures has surged in recent years. A major factor driving this phenomenon is the proliferation of large networks of poorly secured IoT devices. This is exacerbated by the commoditization of the malware development industry, in which tools can be readily obtained in specialized hacking forums or underground markets. However, despite the great interest in targeting this infrastructure, there is little understanding of what the main features of this type of malware are, or the motives of the criminals behind it, apart from the classic denial of service attacks. This is vital to modern malware forensics, where analyses are required to measure the trustworthiness of files collected at large during an investigation, but also to confront challenges posed by tech-savvy criminals (e.g., Trojan Horse Defense). In this paper, we present a comprehensive characterization of Linux-based malware. Our study is tailored to IoT malware and it leverages automated techniques using both static and dynamic analysis to classify malware into related threats. By looking at the most representative dataset of Linux-based malware collected by the community to date, we are able to show that our system can accurately characterize known threats. As a key novelty, we use our system to investigate a number of threats unknown to the community. We do this in two steps. First, we identify known patterns within an unlabeled dataset using a classifier trained with the labeled dataset. Second, we combine our features with a custom distance function to discover new threats by clustering together similar samples. We further study each of the unknown clusters by using state-of-the-art reverse engineering and forensic techniques and our expertise as malware analysts. We provide an in-depth analysis of what the most recent unknown trends are through a number of case studies. Among other findings, we observe that: i) crypto-mining malware is permeating the IoT infrastructure, ii) the level of sophistication is increasing, and iii) there is a rapid proliferation of new variants with minimal investment in infrastructure.

The weakness of the security measures implemented on IoT devices, added to the sensitivity of the data that they handle, has created an attractive environment for cybercriminals to carry out attacks. To do so, they develop malware to compromise devices and control them. The study of malware samples is a crucial task in order to gain information on how to protect these devices, but it is impossible to manually do this due to the immense number of existing samples. Moreover, in the IoT, coexist multiple hardware architectures, such as ARM, PowerPC, MIPS, Intel 8086, or x64-86, which enlarges even more the quantity of malicious software. In this article, a modular solution to automatically analyze IoT malware samples from these architectures is proposed. In addition, the proposal is subjected to evaluation, analyzing a testbed of 1500 malware samples, proving that it is an effective approach to rapidly examining malicious software compiled for any architecture.

High Efficiency Video Coding (HEVC) has become the state-of-the-art video coding standard. It outperforms its predecessors by the introduction of new coding tools, such as the new quadtree-based partitioning scheme called the coding tree unit (CTU), which enables a more flexible partitioning of the input frames. However, selecting the optimal partitioning requires the evaluation of numerous possibilities, which involves long computing times that hinder the applicability of the standard in real-world scenarios. With this in mind, the main focus of this paper is on tackling this complexity by means of a fast partitioning and mode decision algorithm based on a look-ahead stage. This stage performs a preliminary motion estimation that provides the motion costs used to build the least-cost quadtree, which is in turn utilized to conduct the encoding itself. On the basis of this quadtree, the encoder may decide to terminate the partitioning early, or to evaluate additional depth levels adaptively. Furthermore, the encoder may omit some prediction modes according to the costs estimated by the look-ahead stage. A thorough experimental evaluation of the algorithm shows that it can reduce the encoding time by 65.33%, at the expense of only a 1.35% BD-rate for the random access configuration. Combined with a fast inter prediction algorithm, this reduction can rise to 70.55%, while the coding efficiency is maintained at a 1.83% BD-rate. When compared with other related works, these results display an excellent trade-off between the two variables.

In the last few years new devices with different computational capabilities and network connections has emerged, and this leads to the need for more adaptable video streams. The last two video coding standards, namely H.264/Advanced Video Coding and High Efficiency Video Coding, have defined scalable versions of themselves that provide this adaptability by the use of several layers with different levels of quality, frame rates, and resolutions. Moreover, HEVC introduced hybrid scalability, which allows a non-HEVC base layer (e.g., H.264/AVC) in combination with HEVC enhancement layers, what provides backwards compatibility with older devices. Nevertheless, scalable video coding is very computationally expensive, making it necessary to accelerate the video encoding. This paper presents a fast Coding Unit size algorithm for the combination of hybrid and temporal scalabilities that is based on machine learning. Experimental results show that an acceleration of 54% is achieved at the cost of a slight increment in the bit rate.

The High Efficiency Video Coding (HEVC) standard has shown large improvements in coding efficiency compared with previous standards. In particular, HEVC outperforms H.264/MPEG-4 Advanced Video Coding by up to 50% in terms of bitrate reduction for similar perceptual quality. This improvement is the result of the introduction of new coding tools, which enable the representation of data using fewer bits, but at the cost of long computation times. One of the most significant tools introduced by HEVC is the novel quadtree-based structure called the coding tree unit (CTU), which can be subsequently split into coding units (CUs), prediction units (PUs), and transform units (TUs), providing huge flexibility in the encoding. However, selecting the optimal tree partitioning requires the evaluation of a huge number of possibilities, which constitutes the most complex operation for the encoder. In order to tackle this task, this paper proposes a CTU/CU partitioning algorithm based on a pre-analysis stage. This stage performs a fast motion estimation that provides preliminary information to the encoder, including estimate distortion costs, which enables the building of the least-cost quadtree. On the basis of this tree, the evaluation performed by the encoder is restricted to a subset of PUs. After a thorough statistical analysis of numerous CU/PU combinations, we propose two different configurations that prioritize each of the target variables: coding efficiency and time reduction. In the former case, 58.09% of the encoding time can be saved at the cost of a 2.51% increase in Bjøntegaard delta (BD)-rate, while a larger reduction of 63.08% is achieved with a 3.43% increase in BD-rate in the later case.

The High Efficiency Video Coding (HEVC) standard roughly doubles the rate-distortion compression performance of its predecessor, H.264/AVC, at a cost of a high computational complexity. Moreover, intra sequences are commonly used at video editing or post-production, making it necessary a migration from H.264/AVC to HEVC. This paper aims to propose a fast intra transcoding algorithm from H.264/AVC to HEVC.

The demands for high quality multimedia contents and the advent of the Ultra High Definition (UHD) resolution have motivated the development of the High Efficiency Video Coding (HEVC) standard, which outperforms prior standards by up to 50% in terms of coding efficiency. This improvement, however, involves higher computational complexity in the encoder side, making it essential for realtime encoders to implement fast and efficient coding algorithms. In this regard, this paper proposes a pre-analysis algorithm designed to provide coding information to the motion estimation (ME) stage of the encoder. This algorithm, which takes into consideration the particularities of this new standard, makes use of this information to reduce the number of tested reference frames and the number of positions checked in the motion search. As a result, an experimental evaluation of the algorithm shows that it allows reducing the encoding time by 16.10% average with negligible losses in terms of coding efficiency.

High Efficiency Video Coding (HEVC) was developed by the Joint Collaborative Team on Video Coding to replace the current H.264/Advanced Video Coding (AVC) standard, which has dominated digital video services in all segments of the domestic and professional markets for over ten years. Therefore, there is a lot of legacy content encoded with H.264/AVC, and an efficient video transcoding from H.264/AVC to HEVC will be needed to enable gradual migration to HEVC. In terms of rate-distortion (RD) performance, HEVC roughly doubles the RD compression performance of H.264/AVC at the expense of a high computational cost. HEVC adopts a quadtree-based coding unit (CU) block partitioning structure that is flexible in adapting various texture characteristics of images. However, this causes a dramatic increase in computational complexity due to the necessity of finding the best CU partitions. This paper presents an adaptive fast quadtree level decision algorithm that is designed to exploit the information gathered at the H.264/AVC decoder in order to make faster decisions on CU splitting in HEVC using a Naïve-Bayes probabilistic classifier that is determined by a supervised data mining process. The experimental results show that the proposed algorithm can achieve a good tradeoff between coding efficiency and complexity compared with the anchor transcoder; moreover, it outperforms other related works available in the literature.

High Efficiency Video Coding was developed by the JCT-VC to replace the current H.264/AVC standard, which has dominated digital video services in all segments of the domestic and professional markets for over ten years. Therefore, there is a lot of legacy content encoded with H.264/AVC, and an efficient video transcoding from H.264 to HEVC will be needed to enable gradual migration to HEVC. HEVC adopts a quad tree-based Coding Unit block partitioning structure that is flexible in adapting various texture characteristics at the expense of a high computational cost. This paper presents a data-driven probabilistic CTU splitting algorithm that is designed to exploit the information gathered at the H.264/AVC decoder in order to make faster decisions on CU splitting in HEVC. Experimental results show that the proposed algorithm can achieve a good tradeoff between coding efficiency and complexity compared with the anchor transcoder, and, moreover, it outperforms other related works available in the literature.

The rapid emergence and rise of a wide range of electronic devices has led to the need for providing very different levels of video transmission services. The capabilities and performance of these devices determine the type of video streams that they are able to decode. As a way to fulfil their requirements, this paper presents a heterogeneous simultaneous encoding framework of H.264/Advanced Video Coding (AVC) and High Efficiency Video Coding (HEVC) that shares information between encoders in order to reduce the overall encoding time. In this regard, the proposed approach utilizes the H.264/AVC motion vectors of the 16x16 pixels macroblocks as predictors for the HEVC prediction units. As a consequence, the size of the motion estimation search area can be significantly reduced. Results show that an encoding time reduction of 8.95% can be achieved with negligible losses in terms of rate-distortion.

We propose a technique for optimizing the High Efficiency Video Coding (HEVC) encoder by reducing the number of operations performed in the motion estimation stage. The technique is based on the fact that a significant number of motion estimation operations are performed repetitively for the same image samples, but for different block partition sizes. By decoupling the initial motion estimation and the block partitioning into different stages it is possible to remove a considerable number of redundant motion estimation operations. An implementation of the proposed technique on a SIMD optimized version of the HEVC reference encoder shows that, on average, a reduction of 79.02% SAD operations can be achieved, that results in an average reduction of 14.63% of the encoding complexity with negligible impact on the compression efficiency (BD-rate losses of less than 1%).

In this paper, we present precise time and energy models for an intra-only HEVC video encoder. These models are a step forward to understand and estimate the computational complexity and energy demands of an HEVC encoder, which in turn opens the path to finely tuning the computational resources that are dedicated to this purpose. Our models estimate the complexity and energy consumed by the HEVC encoder, in a frame by frame basis, considering two factors: the quantification parameter used to encode each frame and the spatial information of that frame. Our experimental validation demonstrates the accuracy of these models, which report errors that are, on average, below 10% for full HD videos, and 5% for 832 × 480 videos.

HEVC and VP9 are the current state-of-the-art in video compression, thus, it is expected that in the near future these new codecs will replace their predecessors. However, the process of converting video contents compressed with one standard to those using another standard is highly computationally expensive, since a priori the video contents must be decompressed and compressed with the target video encoder. Nevertheless, it is known that some information can be extracted from the decoding process in order to accelerate the encoding process. In this paper, a technique for transcoding from HEVC to VP9 is presented. By using some information extracted from the HEVC decoding process some coding computations will be discarded from being checked in the VP9 encoder. By applying the proposed approaches, a reduction of about 38% of the coding complexity is achieved with acceptable Rate Distortion penalties.

The High Efficiency Video Coding (HEVC) was developed by the Joint Collaborative Team on Video Coding (JCT-VC) to replace the current H.264/AVC standard which has been widely adopted in the last years. Therefore, there is a lot of legacy content encoded with H.264/AVC and an efficient conversion to HEVC is needed. This paper, presents a Fast Quadtree Level Decision (FQLD) algorithm that greatly reduces the complexity of the transcoding process between H.264/AVC and HEVC. The proposal tries to exploit the information gathered at the H.264/AVC decoder to make decisions on Coding Units (CU) splitting in HEVC using a Naïve-Bayes (NB) probabilistic classifier. Experimental results show that the proposed transcoder can achieve a good tradeoff between coding efficiency and complexity.

Simplified Unsymmetrical Multi-Hexagon Search is one of the faster motion estimation algorithms for video coding available in the literature. It achieves a very good tradeoff between computational complexity and coding efficiency. In fact, the H.264/AVC reference software includes it, and it could easily be extended to the new video coding standard: High Efficiency Video Coding. This paper proposes a parallel algorithm which implements the Simplified Unsymmetrical Multi-Hexagon motion search in a graphic processing unit which serves as co-processor for the central processing unit. The results show a negligible rate distortion drop with a speed-up of up to 8× for the motion estimation module compared to the sequential version. Furthermore, the proposed algorithm is evaluated against some related proposals available in the literature, outperforming all of them in terms of time reduction as well as coding efficiency.

High Efficiency Video Coding (HEVC) is the new video coding standard recently approved by ISO and ITU. HEVC allows a bit rate reduction greater than a 50% with respect to its predecessor, the H.264/AVC, offering the same perceptual quality, by means of a set of new tools that have been introduced. Compared with the current state of the art in image coding, such as JPEG, JPEG2000 or the new JPEG XR, the new Intra Frame coding performs a high compression process in the "All-Intra" mode. All these improvements are at expense of a high computational cost, making it considerably difficult to implement in real time. Hence, this paper presents a mechanism that can be used by the RDO algorithm to select the optimal coding block size for Intra-Prediction, by using a data mining classifier, based on a previous training. Experimental results show that the proposed algorithm can achieve a 30% of Time Savings over a wide range of high resolution sequences (Class A, B and F), with a negligible loss of coding efficiency.

The H.264/AVC video coding standard introduces some improved tools in order to increase compression efficiency. One of these new features is the variable block-size motion estimation. Moreover, H.264/AVC defines different prediction structures which include bi-directional predictions and, more recently, the hierarchical one. These structures also includes new Group Of Picture patterns which outperform the traditional ones. In the literature, several techniques have been proposed over the last few years which are aimed at accelerating the traditional inter prediction process, but there are no many works focusing on bidirectional and hierarchical predictions. In this paper, with the emergence of manycore processors or accelerators, a step forward is taken towards an implementation of an H.264/AVC inter prediction algorithm on a Graphics Processing Unit. The results show a negligible rate distortion drop with a time reduction of up to 92% for the complete H.264/AVC encoder.

To incorporate the newly developed High Efficiency Video Coding (HEVC) standard in real-life network applications, efficient transrating algorithms are required. We propose a fast transrating scheme, based on the early prediction of the partition split-flags in P pictures. Using machine learning techniques, the correlation between co-located partitions at different quantizations is investigated. This results in a model which predicts the split-flag and gives the associated prediction accuracy so that the splitting process in the transcoder is optimized. At each partition depth, the model indicates whether the full rate-distortion cost evaluations should be performed at the current depth, or if the partition can be split immediately. Experimental results show that the proposed transcoder reduces the complexity of the transrating process by 76.04%, while maintaining the coding efficiency of a cascaded decoder-encoder.

Wyner-Ziv video coding paradigm provides a framework where most of complexity is moved from the encoder to the decoder. In this way, Wyner-Ziv coding support efficiently multimedia services for low complexity devices which have to capture, encode and send video. Aplications such as mobile phones, sensor, Personal Digital Assistant (PDA) could benefice to this paradigm. On contraty to tradicional video paradigms, the complexity of the decoder is quite high and it should be reduced. This work presents a parallel Wyner-Ziv decoding algorithm in aims to reduce its high complexity. The present approach efficiently distribute the burden of the complexity over the number of cores which are available in the architecture. By using this parallel approach, the decoding time is reduced around 73%. The proposed methods are scalable for any multicore architecture and adaptable for different Wyner-Ziv decoding schemes.

H.264/AVC is the commercial standard currently most in use for video and is based on single view (mono view). Recently, the video community has also standardized an H.264/AVC extension for supporting 3D video sensation which is referred to as Multiview Video Coding (MVC). Like H.264/AVC, MVC includes temporal and spatial prediction but also includes inter-view prediction as well as disparity estimation. Until now, in H.264/AVC the inter prediction techniques have been the most time-consuming tasks and, thus, in MVC with its new interview predictions the encoding time is even higher. This paper proposes a GPU-based algorithm for both temporal and interview prediction. The algorithm proposed is able to perform this complex prediction task by means of an efficient distribution of all the computations over the GPU and also tries to mitigate the sequential dependencies. The approach can achieve a remarkable time reduction of up to 98% with only a negligible loss in coding efficiency. Moreover, this paper shows that the proposed GPU-based algorithm is more energy efficient and thus, requires less energy than the sequential reference.

Nowadays, networks and terminals with diverse characteristics of bandwidth and capabilities coexist. To ensure a good quality of experience, this diverse environment demands adaptability of the video stream. In general, video contents are compressed to save storage capacity and to reduce the bandwidth required for its transmission. Therefore, if these compressed video streams were compressed using scalable video coding schemes, they would be able to adapt to those heterogeneous networks and a wide range of terminals. Since the majority of the multimedia contents are compressed using H.264/AVC, they cannot benefit from that scalability. This paper proposes a technique to convert an H.264/AVC bitstream without scalability to a scalable bitstream with temporal scalability in Main Profile by accelerating the mode decision task of the SVC encoding stage using Machine Learning tools. The results show that when our technique is applied, the complexity is reduced by 87% while maintaining coding efficiency.

SUMMARY H.264/MPEG‐4 part 10 is the latest standard for video compression and promises a significant advance in terms of quality and distortion compared with the commercial standards currently most in use such as MPEG‐2 or MPEG‐4. To achieve this better performance, H.264 adopts a large number of new/improved compression techniques compared with previous standards, albeit at the expense of higher computational complexity. In addition, in recent years new hardware accelerators have emerged, such as graphics processing units (GPUs), which provide a new opportunity to reduce complexity for a large variety of algorithms. However, current GPUs suffer from higher power consumption requirements because of its design. Up to now, GPU‐based software developers have not taken this into account. In this paper, we present a detailed procedure to implement the H.264 motion estimation for a GPU, with the aim of reducing time and, as a consequence, the energy consumption. The results show a negligible drop in rate distortion with a time reduction of over 91.5% on average and it reduces the energy consumption by a factor of 11.78 compared with the reference implementation. Copyright © 2011 John Wiley & Sons, Ltd.

Scalable video coding (SVC) allows encoded bitstreams to be adapted. However, most bitstreams do not incorporate this scalability so bitstreams have to be adapted multiple times to accommodate for varying network conditions or end-user devices. Each adaptation incorporates an additional loss of quality due to transcoding. To overcome this issue, we propose a single transcoding step from H.264/AVC to SVC. Doing so, the resulting bitstream can be freely adapted without any additional quality reduction. Open-loop transcoding architectures can be used for H.264/AVC-to-SVC transcoding with a low complexity, although these architectures suffer from drift artifacts. Closed-loop transcoding, on the other hand, requires a higher complexity. To overcome the drawbacks of both systems, we propose combining both techniques.

Wyner-Ziv video coding presents a new paradigm which offers low-complexity video encoding. However, the Wyner-Ziv paradigm accumulates high complexity at the decoder side and this could involve difficulties for applications which have delay requisites. On the other hand, technological advances provide us with new hardware which supports parallel data processing. In this paper, a faster Wyner-Ziv video decoding scheme based on multicore processors is proposed. In this way, each frame is decoded by means of the collaboration between several processing units, achieving a time reduction up to 71% without significant rate-distortion drop penalty.

H.264/AVC applies a complex mode decision technique that has high computational complexity in order to reduce the temporal redundancies of video sequences. Several algorithms have been proposed in the literature in recent years with the aim of accelerating this part of the encoding process. Recently, with the emergence of many-core processors or accelerators, a new approach can be adopted for reducing the complexity of the H.264/AVC encoding algorithm. This paper focuses on reducing the inter prediction complexity adopted in H.264/AVC and proposes a GPU-based implementation using CUDA. Experimental results show that the proposed approach reduces the complexity by as much as 99% (100x of speedup) while maintaining the coding efficiency.

Distributed Video Coding (DVC) provides a new coding paradigm based on lower complex encoders than decoders. On the decoder side some missed frames have to be estimated by means of available frames and a correlation noise model. In addition, parity bit chunks can be requested to the encoder across the feedback channel to correct the mismatches of these frames. This is an iterative procedure which collets most of the complexity of the decoder. In this work, a novel approach is proposed to parallelize the DVC decoding process in a multicore system. In this way, each bitplane is decoded at the same time by a different core and they exchange information to update the integration limits of the probably model, reaching a time reduction up to 80% with a little bitrate penalty but maintaining the same PSNR.

Mobile to mobile video telephony is being one of the most attractive services that the newest generations of mobile communications system (such as 4G) are offering at the present time. This kind of service needs special requirements in terms of low complexity in both sides of the communication. By using traditional video encoders, such as H.264, those requirements are not satisfied due to the complexity of the encoder. Distributed Video Coding (DVC) deals with the problem of higher complexity constraints encoding algorithms at the expense of increasing the decoder complexity. In order to efficiently support video communications, this paper proposes an improved DVC to H.264 transcoder that maps different kind of GOPs, as well as different GOP lengths, between both paradigms. Moreover, the H.264 motion estimation is adjusted by using information gathered in the first step of the transcoders, offering a considerable reduction of the transcoding total time with a negligible rate-distortion penalty.

Scalable Video Coding (SVC) is a recent extension of the ISO/ITU Advanced Video Coding (H.264/AVC) standard, which allows adapting the bitstream easily by dropping some parts of it named as layers. This adaptation makes possible that the same bitstream meets the requirements for reliable delivery of video to diverse clients over heterogeneous networks using temporal, spatial or SNR scalability, combined or separately. Since the SVC design requires scalability to be provided at the encoder side, the existing contents cannot benefit of it. Efficient techniques for converting contents without scalability to a scalable format are desirable. In this paper, an approach for temporal scalability transcoding from H.264/AVC to SVC is presented and the impact of the GOP size is analyzed. Independently of the GOP size chosen, around a 60% of time saving is achieved while maintaining the coding efficiency. Moreover, this technique could be used to transform an H.264/AVC bitstream without temporal scalability to another H.264/AVC bitstream with hierarchical structures that provides temporal scalability.

Based on our previous efforts, we introduce in this letter a high-efficient MPEG-2 to H.264 transcoder for the baseline profile in the spatial domain. Machine learning tools are used to exploit the correlation between the macroblock (MB) decision of the H.264 video format and the distribution of the motion compensated residual in MPEG-2. Moreover, a dynamic motion estimation technique is also proposed to further speed-up the decision process. Finally, we go a step further on our previous research efforts by combining the two aforementioned speed-up approaches. Our simulation results over more than 40 sequences at common intermediate format and quarter common intermediate format resolutions show that our proposal outperforms the MB mode selection of the rate-distortion optimization option of the H.264 encoder process by reducing the computational requirements by up to 90%, while maintaining the same coding efficiency. Finally, we conduct a comparative study of our approach with the most relevant fast inter-prediction methods for MPEG-2 to H.264 transcoder recently reported in the literature.

This paper proposes an improved Wyner-Ziv to H.264 video transcoder as part of a framework for mobile to mobile video communications. In this scheme, the user devices keep the low complexity constraints by using the Wyner-Ziv encoding and H.264 decoding algorithms. They shift their complexities to the network where the proposed transcoder is allocated. The main goal of the transcoder is to convert the bitstream and reduce the delay efficiently. The results show that the proposed transcoder reduces the complexity by a factor of 95% with a negligible rate-distortion loss.

Distributed video coding (DVC), has been an interesting alternative to the conventional video coding for a number of applications because of its flexibility for designing extremely low complexity video encoders. The performance of DVC can be improved by only modifying the decoder to keep the encoder complexity at the same level. In this paper, we propose a novel modified framework for a DVC codec considering an iterative side information refinement technique. Refinement is performed at the decoder, first with the help of the decoded DC frame and then considering partially decoded frame using previously refined side information. By iteratively refining the side information, a significant improvement has been achieved in the rate distortion performance.

In mobile-to-mobile video communications, both the sender and the receiver devices should not have higher complexity requirements to perform complex video compression tasks. The traditional video coding solutions are not suitable to support this communications due to its extremely complex encoding algorithm. On the other hand, the new Wyner-Ziv video coding paradigm reduces the complexity of the encoder at the expenses of a more complex decoder. In this paper, we propose an improved WZ/H.264 video transcoder to support this mobile-to-mobile communications, using the low complexity Wyner-Ziv encoding and the traditional H.264 decoding to be implemented in the end-user devices. The improved transcoder converts the video from the Wyner-Ziv to H.264 and reuses the motion vectors generated in the Wyner-Ziv decoding, in order to reduce the computational complexity of the motion estimation process in the H.264 encoding. Simulations results show a complexity reduction up to 55% with negligible rate-distortion drop.

The authors develop a decoder/encoder system (transcoder) to solve the consumption constraint in the communications between end-user devices, when a new Wyner–Ziv (WZ)/H.264 framework is defined for being used in mobile-to-mobile environments. This approach is based on leaving to the devices only WZ video encoding and traditional video decoding; the lowest complexity algorithms in both paradigms. The system shifts the burden of complexity to the network, where an improved transcoder that reuses information between both paradigms is allocated. The WZ decoding motion vectors are used to reduce the H.264 motion estimation process. The proposed transcoder offers a complexity reduction up to 60% on average, without any rate distortion drop.

Most of the reported distributed video coding (DVC) architectures have a serious limitation that hinders its practical application. The uses of a feedback channel between the encoder and the decoder require an interactive decoding procedure which is a limitation for applications such as offline processing. On the other hand, the decoder needs an efficient way to estimate the probability of error without assuming the availability of the original video at the decoder. In this paper we continue with our previous works into a more practical DVC architecture which solves both problems based on the use of machine learning. The proposed approach is based on extracting the relationships that exist between the residual frame and the number of requests over this feedback channel. We apply these concepts to pixel-domain Wyner-Ziv coding demonstrating significant savings in bitrates with a little loss of quality.

Distributed video coding has become increasingly popular in recent years among the researchers in video coding due to its attractive and promising features. DVC proposed a dramatic structural change to video coding by shifting the majority of complexity conventionally residing in the encoder towards the decoder. Nevertheless, these kinds of architectures have some serious limitations that hinder its practical application. The uses of a feedback channel between the encoder and the decoder requires an interactive decoding procedure which is a limitation for certain applications such as offline processing. On the other hand, the decoder needs an efficient way to estimate the probability of error without assuming the availability of the original video at the decoder. In this paper we investigate a first approximation to solve both problems based on the use of machine learning to extract the knowledge that exits between the residual frame and the number of requests over this feedback channel. Exploiting this correlation gives us a more practical architecture without higher complexity encoders. We apply these concepts to pixel-domain Wyner-Ziv coding and the results show a loss of 0.21 dB in the rate-distortion performance.

Distributed video coding (DVC) is an increasingly popular approach among the researchers in video coding during past few years due to its attractive and promising features. In DVC, the majority of the computational complexity has been shifted from encoder to the decoder in comparison to its conventional counterparts, including MPEG and H.26 x enabling a dramatically low cost encoder implementation. Side information generation, carried out at the decoder, is a major function in the DVC coding algorithm and plays a key-role in determining the performance of the codec. In this paper, a novel iterative refinement technique is proposed for the side information generation process. Simulation results of the proposed technique depict a consistent improvement in performance in comparison to the state-of-the-art in pixel domain DVC.