In today's high-speed/high-density very large scale integrated (VLSI) circuit designs with coupled interconnect lines, signal transients are strongly correlated with the input switching patterns. Signal-delay variations due to the input-switching patterns may be more than /spl plusmn/50% of the delay of an isolated single line. Thus, blind static timing-analysis techniques without consideration of the detailed switching effects may not be accurate enough to meet tight timing margins for today's deep submicron (DSM)-based VLSI circuits. In this paper, the signal-transient responses of multicoupled interconnect lines due to various input-switching patterns are analyzed in terms of the effective capacitances and effective inductances. Thereby, the critical delay line of multicoupled interconnect lines is decoupled into an effective single-isolated line. With the proposed novel decoupling technique for multicoupled interconnect lines, the accurate dynamic delay of strongly coupled interconnect lines can be readily determined with physical layout information. For example, in switching patterns, the paper shows that the signal delays calculated by using the effective single-line models have excellent agreement with SPICE simulations using the generic coupled interconnect circuit models. That is, the accuracy for both RC-dominant lines and RLC lines is within 10% error (but often within 5% error). Thus, without any significant modification of existing IC computer-aided design frameworks, the technique can be directly as well as usefully employed for accurate timing verification of DSM-based VLSI designs.

Novel signal integrity verification models and algorithms for inductance-effect- prominent RLC interconnect lines are developed by using a traveling-wave-based waveform approximation (TWA) technique. The multicoupled line responses are decoupled into the eigenmodes of the system in order to exploit the TWA technique. Then, the response signals are mathematically represented by the linear combination of each eigenmode response based on TWA, followed by reporting the signal integrity models and algorithms for the multicoupled lines. The signal integrity of VLSI circuit interconnects is complicatedly correlated with input signal switching-patterns, layout geometry, and termination conditions. It is shown that the technique can be efficiently employed for complicated multicoupled interconnect lines with various termination conditions and the signal transients based on the technique have excellent agreement with SPICE simulations. Thus, with the proposed technique, the switching-dependent signal delay, crosstalk, ringing, and glitches of the inductance-effect-prominent RLC interconnect lines can be accurately as well as efficiently determined.

Today's high-speed very large scale integration interconnects are becoming inductively dominated (moderate Q) resistance-inductance-capacitance (RLC) transmission lines. The time-domain system responses of RLC interconnect lines driving load capacitances cannot be accurately represented by using a finite number of poles with exception for a particular case of RC-time-constant-dominant (low Q) RLC systems. In this paper, a new traveling-wave-based waveform approximation technique is presented. The method suggests that a steady-state traveling wave is approximately determined by a three-pole approximation technique. Then the time-domain response of the system can be accurately determined by using the traveling waves that are modeled by multiple reflections. The signal delay models of the RLC interconnect lines are derived as a closed form. The technique is verified by varying the source resistance, load impedance, and transmission line circuit model parameters of several RLC lines. The results show excellent agreement with HSPICE simulation results. That is, approximately 5% error in a 50% delay calculation can be achieved.

As very large scale integration (VLSI) circuit speed rapidly increases, the inductive effects of interconnect lines strongly impact the signal integrity of a circuit. Since these inductive effects make the signal integrity problems much more serious as well as intricate, they become one of the critical issues in today's high-speed/high-density VLSI circuit design. In this paper, a generalized traveling-wave-based waveform approximation (TWA) technique is presented which can be accurately as well as efficiently employed for the signal integrity verification of the inductively dominated (moderate Q) multicoupled RLC transmission line system. The technique is composed of three steps. First, the signals in the multicoupled (n-coupled) transmission line system are decoupled into n-isolated eigen-modes (i.e., basis vectors). Next, the slow-transient low-frequency characteristics of the system response are determined, approximately, in the frequency-domain by using the dominant poles of the basis vectors. Finally, the fast-transient high-frequency characteristics of the system response are calculated in the time domain by using the traveling wave characteristics of the basis vectors. It is shown that the time-domain responses of the multicoupled RLC transmission line system can be accurately as well as efficiently modeled with the generalized TWA technique. Then, in inductance-dominant multicoupled interconnect networks, switching-dependent signal integrity, i.e., signal delay, crosstalk, ringing, and glitches are investigated extensively with the proposed technique.

A new fast and accurate capacitance determination methodology for intricate multilayer VLSI interconnects is presented. Since a multilayer interconnect structure is too complicated to be directly tractable, it is simplified by investigating charge distributions within the system. The quasi-three-dimensional (3-D) capacitances of the structure are then determined by combining a set of solid-ground-based two-dimensional (2-D) capacitances and shielding effects that can be independently calculated from the simplified structure. The shielding effects due to the neighboring lines of a line can be analytically determined from the given layout dimensions. The solid-ground-based 2-D capacitances can also be quickly computed from the simplified structure. Thus, the proposed capacitance determination methodology is much more cost-efficient than conventional 3-D-based methods. It is shown that the calculated quasi-3-D capacitances have excellent agreement with 3-D field-solver-based results within 5% error.