This paper describes optimizations for the critical maximum exponent and alignment operations, with scalability for many-term fused floating-point dot-product units. The impact of these optimizations is quantified for up to 32-term BFloat16 weight/activation inputs with single-precision dot-product output, targeted for machine learning accelerators. Area and energy efficiency results are compared across performance targets, design parameters, and data statistics.

Capturing the dynamism that pervades biological systems requires a computational approach that can accommodate both the continuous features of the system environment as well as the flexible and heterogeneous nature of component interactions. This presents a serious challenge for the more traditional mathematical approaches that assume component homogeneity to relate system observables using mathematical equations. While the homogeneity condition does not lead to loss of accuracy while simulating various continua, it fails to offer detailed solutions when applied to systems with dynamically interacting heterogeneous components. As the functionality and architecture of most biological systems is a product of multi-faceted individual interactions at the sub-system level, continuum models rarely offer much beyond qualitative similarity. Agent-based modelling is a class of algorithmic computational approaches that rely on interactions between Turing-complete finite-state machines--or agents--to simulate, from the bottom-up, macroscopic properties of a system. In recognizing the heterogeneity condition, they offer suitable ontologies to the system components being modelled, thereby succeeding where their continuum counterparts tend to struggle. Furthermore, being inherently hierarchical, they are quite amenable to coupling with other computational paradigms. The integration of any agent-based framework with continuum models is arguably the most elegant and precise way of representing biological systems. Although in its nascence, agent-based modelling has been utilized to model biological complexity across a broad range of biological scales (from cells to societies). In this article, we explore the reasons that make agent-based modelling the most precise approach to model biological systems that tend to be non-linear and complex.

Moore's Law will continue providing abundance of transistors for integration, only to be limited by the energy consumption. Near threshold voltage (NTV) operation has potential to improve energy efficiency by an order of magnitude. We discuss design techniques necessary for reliable operation over a wide range of supply voltage---from nominal down to subthreshold region. The system designed for NTV can dynamically select modes of operation, from high performance, to high energy efficiency, to the lowest power.

In this paper, we propose a new circuit technique for on-chip communication, the edge encoding technique, to reduce the energy consumption in multi-cycle interconnects. Both average and worst-case energy are reduced by desynchronizing the edges of rising and falling transitions. In a 1.2 V 65-nm CMOS technology, the proposed approach achieves up to 34% energy reduction with no latency overhead over optimally designed conventional busses due to coupling capacitance reductions. The technique further reduces energy consumption by 39% with iso-throughput at the expense of one-cycle latency. Energy savings are shown to be both larger and more robust to process, voltage, and temperature variations than previous techniques.

This paper describes an alternate repeater insertion technique that uses correct-by-construction polarities to reduce worst-case miller coupling factor (MCF) across any multiple segmented portion of a repeated bus. Simple static CMOS circuits with nominal p-n skews allow drop-in replacement while maintaining robust operation. For the same repeater area, number and position of repeaters of conventional busses, this technique simultaneously reduces delay by 15%, energy by 29% and peak current by 12% for 2-8 mm on-chip busses in 1.2 V, 65 nm CMOS. Under equal delay constraints, the proposed technique reduces worst-case energy and peak current by 39% and 36%, respectively. The technique easily extends to shared busses for multi-core designs and shows a 41% improvement in energy-efficiency for a 10 mm 5 GHz multi-cycle on-chip core-to- core bus.

In this paper, we propose a new edge encoding technique to reduce the energy consumption in multi-cycle interconnects. Both average and worst-case energy are reduced by desynchronizing the edges of rising and falling transitions. In a 1.2V 65nm CMOS technology, the approach achieves up to 31% energy reduction with no latency overhead over optimally designed conventional busses due to coupling capacitance reductions. The technique further reduces energy consumption by 38% with iso-throughput at the expense of one-cycle latency. Energy savings are shown to be more robust to process variations than previous techniques.

On-chip buses are typically designed to meet performance constraints for worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching pattern. This can result in significant performance slack at more typical operating conditions. We propose a dynamic voltage scaling (DVS) technique for buses, based on a double sampling latch which can detect and correct for delay errors without the need for retransmission. The proposed approach recovers the available slack at non-worst-case operating points through more aggressive voltage scaling and track changing conditions by monitoring the error recovery rate. Voltage margins needed in traditional designs to accommodate worst-case performance conditions are therefore eliminated, resulting in a significant improvement in energy efficiency. The approach was implemented for a 6 mm memory read bus operating at 1.5 GHz (0.13 /spl mu/m technology node) and was simulated for a number of benchmark programs. Even at the worst-case process and environment conditions, energy gains of up to 17% are achieved, with error recovery rates under 2.3%. At more typical process and environment conditions, energy gains range from 35% to 45%, with a performance degradation under 2%. An analysis of optimum interconnect architectures for maximizing energy gains with this approach shows that the proposed approach performs well with technology scaling.

We propose a novel buffer circuit that allows on-chip signaling for dual-VDD systems at the lower supply (VDDL) with a higher performance and smaller area than the standard buffer. The proposed dual-VDD buffer uses a pull-up PMOS connected to the higher supply (VDDH) rail in parallel with a standard buffer connected to VDDL. The VDDH pull-up PMOS turns on only briefly during a rising transition to aid the VDDL pull-up PMOS but avoids contention at steady state. The higher current drive with the VDDH PMOS allows a favorable trade-off of a considerable reduction in the VDDL buffer size for a small increase in the VDDH PMOS size. This trade-off is especially useful for meeting aggressive delay targets with the lower supply and allows the dual-VDD buffer to increase performance (up to 22%) compared to the standard buffer at VDDL, while still consuming less energy than VDDH signaling. The dual-VDD buffer also achieves gains in energy (up to 17%), buffer area (up to 56%) and peak current (up to 33%) at delay targets that can be met with standard buffers using VDDL.

We propose various low-latency spatial encoder circuits based on bus-invert coding for reducing peak energy and current in on-chip buses with minimum penalty on total latency. The encoders are implemented in dual-rail domino logic with interfaces for static inputs and static buses. A spatial and temporally encoded dynamic bus technique is also proposed for higher performance targets. Comparisons to standard on-chip buses of various lengths with optimal repeater configurations at the 130-nm node show the energy-delay and peak current-delay design space in which the different encoder circuits are beneficial. A 9-mm spatially encoded static bus exhibits peak energy gains beyond that achievable through repeater optimization for a single-cycle operation at 1 GHz, with delay and energy overhead of the encoding included. For throughput-constrained buses, the spatially encoded static bus can provide up to 31% reduction in peak energy, while the spatially and temporally encoded dynamic bus yields peak current reductions of more than 50% for all bus lengths. The encoder circuits show good scaling properties since the performance penalty from encoding decreases with scaled interconnects.

We propose various low-latency spatial encoder circuits based on bus-invert coding for reducing peak energy and current in on-chip buses with minimum penalty on total latency. The encoders are implemented in dual-rail domino logic with interfaces for static inputs and static buses. A spatial and temporally encoded dynamic bus technique is also proposed for higher performance targets. Comparisons to standard on-chip buses of various lengths with optimal repeater configurations at the 130nm node show the energy-delay and peak current-delay design space in which the different encoder circuits are beneficial. A 9mm spatially encoded static bus exhibits peak energy gains beyond that achievable through repeater optimization for a single cycle operation at 1GHz, with delay and energy overhead of the encoding included. For throughput constrained buses, the spatially encoded static bus can provide up to 31% reduction in peak energy, while the spatially and temporally encoded dynamic bus yields peak current reductions of more than 50% for all bus lengths.

In this paper, we propose a new circuit structure, the transition aware global signaling (TAGS) receiver, that detects transitions at arbitrary switch points. The major performance advantage of this circuit occurs when it switches before the 50% point in the input transition. The TAGS receiver stores the next state of the line while quiet. Upon detection of a transition at the end of the line the output is temporarily driven by the stored next state. Transitions at the output of the receiver are much faster than at the end of the line since they are generated locally. Its ability to detect transitions before a standard inverter and locally generate them at its output, allows its use at the end of long interconnects with fewer repeaters for the same delay as the standard repeater paradigm. The need for fewer repeaters with the TAGS scheme results in lower power consumption for on-chip global communication, while also reducing the placement overhead involved with large buffer blocks. This is shown in the context of bus optimizations, where TAGS achieves up to 50% reduction in power compared to standard repeaters. In an industrial 0.13-/spl mu/m CMOS process, TAGS receivers enable 8-mm-long buses at 1.5-GHz clock rates without repeaters, while the traditional scheme required three repeaters on the line. An extensive analysis of crosstalk noise in the bus environment shows that TAGS can handle the noise levels produced in typical bus structures. Also, the variation of delay in the bus structure under worst-case power supply noise for the TAGS scheme is typically smaller than the delay variation using the standard repeater scheme.

A new shielding scheme, active shielding, is proposed for reducing delays on interconnects. As opposed to conventional (passive) shielding, the active shielding approach helps to speed up signal propagation on a wire by ensuring in-phase switching of adjacent nets. Results show that the active shielding scheme improves performance by up to 16% compared to passive shields and up to 29% compared to unshielded wires. When signal slopes at the end of the line are compared, savings of up to 38% and 27% can be achieved when compared to passive shields and unshielded wires, respectively.

We highlight several fundamental challenges to designing high-performance integrated circuits in nanometer-scale technologies (i.e. draRita Glover, EDA Today, L.C.wn feature sizes < 100 nm). Dynamic power scaling trends lead to major packaging problems. To alleviate these concerns, tMarc Halpernhermal monitoring and feedback mechanisms can limit worst-case dissipation and reduce costs. Furthermore, a flexible multi-Vdd + multi-Vth + re-sizing approach is advocated to leverage the inherent properties of ultra-small MOSFETs and limit both dynamic and static power. Alternative global signaling strategies such as differential and low-swing drivers are recommended in order to curb the power requirements of cross-chip communication. Finally, potential power delivery challenges are addressed with respect to ITRS packaging predictions.