This paper proposes an Ambient-Adaptive Voltage Scaling (AAVS) driver for SPAD arrays that maintains quasi-linear photon detection across a wide range of illumination levels. The proposed system integrates an Adaptive Feedback-Controlled (AFC) V${}_{\mathbf {EX}}$modulator that continuously senses photon flux to regulate the excess bias voltage (V${}_{\mathbf {EX}}$) relative to the actual breakdown voltage (V${}_{\mathbf {BD}}$), coupled with a hybrid boost converter featuring adaptive V${}_{\mathbf {EX}}$calibration to generate 27.1–27.6V with sub-millivolt ripple. Measurement results demonstrate a 131 dB dynamic range ($10^{10}$–$10^{17}$photons/cm${}^{2}\cdot $s), 92.3% peak efficiency, and robust scalability supporting 128-SPAD arrays. The AAVS architecture enhances sensitivity under low-light conditions while effectively preventing saturation in high-light scenarios.

In recent years, the complexity of neural network (NN) models has increase continuously, resulting in a substantial increase in multiply-accumulate (MAC) operations. Therefore, the need for area- and power-efficient DRAM compute-in-memory (CIM) designs has become a pressing issue. The proposed CIM design uses the reverse rotating charge sharing (RRCS) technique to save 79% of silicon area compared to conventional designs. In addition, the use of the proposed low-threshold prediction technique can reduce analog-to-digital converter (ADC) calculations by 25% and ADC power consumption by 17%. Energy efficiency and area reduction are 10x and 1900x, respectively, higher than previous CIM designs.

The conventional capacitor-switch-inductor (C-S-L) topology suffers from significant conduction loss and sluggish transient response due to the series power switches conduction inherent in its structure. To address these limitations, the proposed rotated hybrid converter adopts a rotated mechanism and parallel conduction within the capacitor-two-switch-inductor (C-2S-L) topology, effectively reducing current stress on components. This approach enhances efficiency while mitigating the effects of parasitic inductance from bond wires. During transient conditions, all C-2S-L stages can be simultaneously activated, enabling a near-full duty cycle (D). Experimental results demonstrate a minimal undershoot of 96 mV and a fast settling time of 0.92 μs during a load step from 2 A to 10 A within 20 ns. Additionally, the converter integrates phase shedding, dynamically adjusting the number of active phases according to load conditions to optimize efficiency across a broad load range. Therefore, the proposed C-2S-L topology achieves a peak efficiency of 92.6% at an output voltage (VOUT) of 1.2 V and a load current (ILOAD) of 3A.

This paper proposes a flying-capacitor sharing dynamic four-path (FCSD-4P) hybrid converter, designed to achieve a duty cycle (D) ranging from 0% to 100%, addressing the conventional limitation of D2. In a 6V to 1.8V conversion, the converter achieves a peak efficiency of 94.2%.

This paper proposes a two-step down converter based on Pseudo 4-Phase Mutual Operation (P4MO) that uses inductors and coupled inductors to regulate output voltage (VOUT). By doubling the inductor current slew rate, the design reduces the intermediate capacitor (CINT) at VINTby nearly 50%. Additionally, conduction losses in the dual-output triple step-down (DOTS) input stage are reduced by approximately 30%. Moreover, a delayed feedback PWM technique further reduces the VINTripple by about 20%. An integrated soft turn-off circuit minimizes voltage variations at VOUTto less than 2 mV during phase shedding. Experimental results validate the design’s performance, showing a peak efficiency of 93.1%, undershoot of 106 mV with a recovery time of 1.9 μs for a load step transition from 1 A to 20 A, and a transient performance of 5.58 mV/A.

In this paper, the proposed multi-phase (MP) bidirectional dual Gallium-Nitride (GaN) controlled rectifier (GCR) uses dual GCR with the pre-charge technique to reduce third quadrant operation by minimizing dead time to 0.12ns and 0.13ns, and lowering the negative VDS to −0.6V and −0.8V in buck and boost operation, respectively. This work is the first research for monolithic bidirectional energy transfer with a two-switch-only topology. With the help of MP-accelerated current control and the GCR dynamic ramp generator, the voltage variation on the high-voltage (HV) side and low-voltage (LV) side can be reduced to less than 50mV and to 40mV, respectively, during buck and boost operation transitions. Moreover, the recovery time is effectively reduced and current balance between the four phases can be achieved within 7 cycles (=350ns). The peak efficiency is as high as 95.5% and 94.2% in buck and boost operation, respectively.

This paper proposes an isolated gate driver that incorporates an enhanced common-mode transient immunity (CMTI) technique to effectively suppress common-mode transient (CMT) noise. Additionally, the approach leverages the CMT noise to enable on-the-fly deadtime (DT) control at the transmitter. Experimental results demonstrate the DT jitter compensation circuit reduces high-frequency carrier (500 MHz) jitter by 10.6%, the efficiency is improved by 11.5%, and the CMTI is improved from 184 kV/μs to 208 kV/μs.

This paper proposes a two-phase hybrid buck-boost converter, which meets the criteria of USB PD 3.1, with an auxiliary inductor LAUX to achieve soft switching by the zero voltage switching (ZVS) technique at light loads. Besides, two interleaving phases can reduce the inductor current to half of that conventional design. Benefiting from a coupled inductor with a negative mutual inductance (M$_{\mathrm {L(AC)}}$becomes small to achieve low output voltage ripple due to large equivalent inductance Leq in a steady state. Based on the loading current, the phase shedding can change the number of driving phases for high efficiency. Moreover, a transient enhancement circuit is proposed to speed up transient response time. The proposed circuit achieves the maximum inductor current ripple reduction of 9.09% and the maximum P$_{\mathrm {AC\_loss}}$reduction of 17.36% at D=0.5. Experimental results show 96.1% peak efficiency. In the case of the load step 0.5A to 5A, the recovery time and undershoot are reduced to$10.7\mu $s and 133mV, respectively, and in the case of the load step 5A to 0.5A, the recovery time and overshoot are reduced to$9.4\mu $s and 147mV, respectively.

This paper proposes a series-parallel bond wire auxiliary fully integrated step-up switched-capacitor (SC) converter with conversion ratio expansion to improve the trade-off between power loss and output voltage ripple. The series-parallel switching strategy reduces the burden of delivering charges in a 1:2 SC and also extends the output-input voltage ratio range. In addition, the$\text{L}_{\mathbf {BOND}}$mismatch calibration (LMC) technique can eliminate the mismatch between bond wires. Moreover, the binary flying capacitor scaling technique automatically optimizes the capacitance of the flying capacitor to ensure a well-controlled output voltage ripple over a wide load range. With only 250pF total capacitors in use, the experimental results show a well-controlled ripple under 23.86mV and efficiency greater than 75% over a load range of 1mA to 20mA. Furthermore, this technique has a smooth efficiency profile within an input voltage level of 0.63V to 0.9V with a peak efficiency of 85% and an output voltage of 0.95V.

this paper proposes a new dual-mode low-dropout linear regulator without external capacitors, which includes three error amplifiers, an offset voltage generator, a mode decision circuit, and a pre-biasing load transient enhancement circuit. The chip uses a 28nm CMOS process to verify the advantages brought by the architecture of this work. The measurement results show that the output voltage has a negligible undershoot and overshoot (both less than 5mV) during mode transition. In load transient response, due to the use of pre-charge technique, the output voltage undershoot and overshoot are reduced by 45.2% and 36%, respectively. Finally, this architecture achieves FoM to be close to 1fs.

the proposed distributive digital low dropout (DLDO) regulator utilizes the triple binary successive approximation recursive (SAR) control algorithm for fast transient response. In addition, the body voltage control (BVC) can be used to expand the least significant bit (LSB) to enhance the accuracy. In case of load transients, the BVC can further increase or decrease the driving capability for fast transient response. Experimental results show that the voltage droop can be less than 72 mV at $F_{\text{CLK}}=100 \text{MHz}$, accomplishing a fast settling time of 3.6 ns. Burst cells and lossless cells can maintain overshoot below 68 mV with the settling time of 11.2 ns. The BVC technique reduces output voltage ripple to less than 0.4 mV in the steady-state.

Ultra-low quiescent current ($I_{Q}$) low-dropout regulator is the only solution for compact size Internet of Things (IoT) electronic devices. This paper presents an ultra-low$I_{Q}$low dropout regulator, including low$I_{Q}$error amplifier (EA) compensated by the adaptive current control (ACC), low leakage feedback network, low$I_{Q}$current comparator, analog transient enhancement (ATE), and digital transient enhancement (DTE). The chip was fabricated in a standard$0.5~\mu \text{m}$CMOS process. Measurement results show the current peak efficiency of the LDO is as high as 99.99%. Besides, owing to ATE and DTE circuits, when the load current changes from 1mA to 50mA with a 10 ns edge time, the measured undershoot and overshoot voltages are 75 mV and 50 mV, respectively, with the recovery time ($T_{R}$) of 60 ns and 80 ns, respectively, where the best 0.003 ps FoM is achieved.

The series stacked (SS) FinFET structure is used in digital low dropout (DLDO) regulators to withstand high input voltages and implement dynamic voltage scaling (DVS) technique with minimum energy point (MEP) technique. Through an additional delay consideration in MEP, both energy reduction and performance of the Cortex M0 processor can achieve 34.5pJ/cycle at 0.5V. Maximum energy reduction is about 37.5% and the supplying voltage varies from 0.4V to 0.775V with a search time of 2.5μs for each voltage step. The proposed SS-DLDO has fast settling time and low output voltage ripple of 1.5μs and 5mV, respectively.

This paper proposed MicroLED virtual pixel array design and driver. The proposed virtual pixel array effectively increases the pixels per inch (PPI) while having a relatively low ghosting. The push-pull supply buffer in the proposed driver is compensated by the dynamic Miller compensation (DMC) technique to reduce the ghosting by 50%-73%. Four times screen resolution can be obtained compared to conventional designs. 95% high efficiency microLED driver has the lowest 45μW power consumption.

This paper presents a fast transient low-dropout regulator (LDO) with bulk modulation technique and dynamic transient boost circuit (TBC) for system-on-chip (SoC) applications. The conventional bulk modulation and dynamic biasing techniques failed to obtain low quiescent current and better stability at no-load conditions. The proposed bulk modulation technique implemented by using only one error amplifier with two different gain stages to achieve the small quiescent current and to obtain good regulation with better driving capability. The proposed TBC combines the dynamic biasing and output compensation techniques to enhance the transient response of LDO drastically. The proposed design is simulated in the 40nm LVT CMOS process shows that the LDO delivers 1V output voltage and consumes 15μA of quiescent current with the supply voltage of 1.1V. When the load current changes from 100nA to 10mA with a large slew rate of 200ps, undershoot and settling time are 450mV and 8ns respectively. Compared to LDO without TBC, the proposed LDO offers good stability, better driving capability, ~10× less undershoot and ~10× fast settling time.

This paper proposes an active clamp flyback (ACF) converter with GaN devices. Compared to Si FETs, when the main GaN FET is at full zero voltage switching (FZVS), maximum switching loss reduction can be achieved. Thus, the use of dynamic resonant period control (DRPC) technique to achieve fast ZVS can reduce 87% of the transformer leakage inductance energy loss on the active resonant circuit (ARC). When the load changes, the DRPC technique dynamically adjusts the auxiliary switch on-time to prevent large voltage stress on the primary side components. At full load, the leakage energy loss can be reduced, thereby transferring more energy to the secondary side with an efficiency of up to 94%.

This paper presents a LDO-controlled current sensor for accelerating constant on-time (COT) switching regulators (SWRs) for high efficiency envelope tracking power modulators (ETSMs) for RF power amplifiers (RF PAs). The proposed LDO-controlled current sensor controls the feedback loop of the SWR, rather than the traditional current sensing technique, in the case of fast envelope tracking. The LDO regulator behaves as the master to rapidly trigger the SWR as a slave energy provider to rapidly deliver the average energy to the RF PA for high efficiency. The experimental results show that the test chip fabricated in 0.18μm CMOS process can accurately track the RF envelope signal, and the peak efficiency is 86.7% when the power is 0.95W.

It is crucial in near field communication (NFC) controllers for power source transferred from mutual induction of coils when the devices are battery-off. NFC devices can be operated at the condition of low battery or even battery-off due to the requirement of payment any time. Thus, the proposed wireless power transfer (WPT) power supply can have high efficiency due to the remove of reverse leakage current by the digital reverse current self-calibration (DRCS). NFC standards including A, B, and F can be continuously supplied by the WPT supply system. The WPT power supply with the DRCS technique was fabricated in 0.25μm CMOS process can rectify AC source from induction of magnetic field to unregulated DC voltage source and to supply power the NFC controller through low dropout regulator (LDR). Moreover, test chip achieves as high as 92% voltage conversion ratio and 89.4 % power conversion efficiency (PCE) due to reduction of unnecessary current loss.

The non-isolated buck topology for LED driver is proposed to reduce volume and cost without the need of large transformer. Besides, in the entire universal range of AC input voltage, the proposed self-adjusted feed-forward control (SAFFC) technique ensures small variation in the LED current. The auto-tracking off-time control (ATOTC) technique is also adopted to adjust the off time to guarantee the current accuracy is better than that of the peak current control (PCC) technique while and the efficiency is better than that of the hysteresis current control (HCC) technique. Test chip fabricated in VIS 0.5μm 700V ultra-high voltage (UHV) process demonstrates power factor higher than 0.97, averaged 95% high accuracy, and 95% high efficiency.

This paper proposed the adaptive knee voltage detection (KVD) technique to improve the output voltage accuracy of the primary side regulator. Owing to the insertion of the snubber circuit for reducing overshoot voltage, conventional KVD technique fails to get the output voltage information and thus to deteriorate the output voltage accuracy. Analysis of the snubber circuit and the resonance of the primary side can determine the band-pass filter in the proposed AKVD technique to get high accuracy output information without being affected by any kinds of resonances. Test chip designed in VIS 0.5μm BCD process demonstrates the accuracy of the output voltage higher than 99%. Besides, any abnormal detection won't happen and thus the output ripple can be kept low.

Implantable devices like artificial cardiac pacemakers are generally used to control irregular pulses of heart. For 10-year usage, high accuracy supply voltage is essential with the unavoidable aging of the power system to achieve near-natural beat rhythm. A Self-Calibration DC-DC Buck converter (SC-Buck) is proposed to achieve high output voltage accuracy by eliminating offset caused by mismatch of process, voltage and temperature (PVT). Furthermore, the discontinuity which affects transient performance in conventional offset cancellation is also overcome. Large area occupation, which is required to decrease mismatch in conventional operational amplifier, can be largely decreased according to Monte Carlo analysis. Without trimming process, the proposed SC-Buck technique achieves high accuracy for long-term usage (years) and low cost. The test chip fabricated in UMC 28nm CMOS process proves the output voltage accuracy of 97% since the mismatch of error amplifier can be suppressed from 122% to 1%.

Light-emitting diode lighting system with the proposed pseudo-sine-current controller removes most of the external passive components, which include inductor, electrolytic capacitor, freewheel diode, blocking diode, and the bleeding circuit for Triac dimming control, for low cost and small volume. Delay-lock loop control can ensure the in-phase operation of ac input voltage and current for high power factor (PF) and low total harmonic distortion (THD). In addition, redundant power loss in Triac dimming control is eliminated to get a high efficiency of 85%. Furthermore, a high PF of 0.997 and a low THD of 7.74% are also achieved owing to in-phase line voltage and current.

This paper repots an optimum on-time (OOC) control with predicting correction technique (PCT) for ripple-based buck converter. The switching frequency (FSW) variation is analyzed with completely considering the parasitic resistances of the components and devices. The proposed converter achieved nearly constant switching frequency over a wide load range without extra clock controlled circuits and current sensing circuits. The parameters of the parasitic resistances almost cause no influence and no restriction on FSWperformance. Actually, only the input voltage is necessary to predict the optimum on-time, and this work benefits the decease on total pin numbers. The simulation results demonstrate 0.375% ΔFSW/FSWand 2kHz/A ΔFSW/ΔILOADover 1.5A load current change. Consequently, pseudo constant FSWwith known noise spectrum strongly benefits the solution of electromagnetic interference (EMI) issue for system-on-chip (SoC).

An increased damping resistor (IDR) replaces high-order loop filter to simply reduce the total harmonic distortion (THD) of Class-D audio amplifier. Besides, cross offset cancellation (COC) technique minimizes the system offset voltage to avoid dc current flows to the speaker in the bridge tied load (BTL) structure. Furthermore, variable switching frequency characteristic in self-oscillating modulation spreads the electro-magnetic interference (EMI) impact out on the output frequency spectrum. Experimental results demonstrate that the proposed Class-D amplifier can deliver 0.55W to the 8Ω load with a 3.3V supply voltage with 150-nm CMOS process. The power efficiency is over 90% and the output THD is smaller than 0.01% (80dB).

This paper presents a dual-level dual-phase pulse-width modulation (DLDP PWM) Class-D audio amplifier circuit which enhance amplifier linearity and reduce distortion. The proposed DLDP PWM Class-D audio amplifier includes two sets of non-overlapping triangular waves, each at its respectful offset levels. Each set of triangular waves is composed of two 180° out-of-phase triangular waves. The differential power stage consists of 8 power transistors, with voltage swings up to +/- 6V. Simulated results shows that the proposed DLDP PWM Class-D audio amplifier features an SNR up to 105 dB, and the THD is suppressed below 0.001 %, with the 3rd harmonic below -102 dBV.

To cope with monolithic controller replicas and the current unbalance situation in multiphase converters, a pseudo-ramp current balance technique is proposed to achieve time-multiplexing current balance in voltage-mode multiphase DC-DC buck converter. With only one modulation controller, silicon area and power consumption caused by the replicas of controller can be reduced significantly. Current balance accuracy can be further enhanced since the mismatches between different controllers caused by process, voltage, and temperature variations are removed. Moreover, the offset cancellation control embedded in the current matching unit is used to eliminate intrinsic offset voltage existing at the operational transconductance amplifier for improved current balance. An explicit model, which contains both voltage and current balance loops with non-ideal effects, is derived for analyzing system stability. Experimental results show that current difference between each phase can be decreased by over 83% under both heavy and light load conditions.

This paper proposes a current-mode synthetic control (CSC) technique for the design of boost converters to overcome the difficulty in designing a current-ripple hysteresis boost converter and to maintain high conversion efficiency over a wide load range. The CSC technique has a high accuracy because of the additional voltage path through the error amplifier. A smooth load transient response is maintained when the operation transits from continuous conduction mode with a nearly constant switching frequency to discontinuous conduction mode with a load-dependent switching frequency. Generally, ripple performance, light-load efficiency, and switching frequency are traded off in the design of hysteresis control regulator. In this paper, a balance among the load-dependent switching frequencies at light loads results in high power conversion efficiency compared with conventional pulsewidth modulation converter and attains compact ripple performance. The experimental results show that the output voltage ripple can be kept ${<;}{\rm 50}~{\rm mV}$ over a wide load current range from 10 to 400 mA, where as power conversion efficiency is maintained at 78% at a load current of 10 mA when the switching frequency is decreased from 5 to 2 MHz.

The proposed sinusoidal-wave synthesis (SWS) and the optimized THD control (OTC) improve power factor (PF) and total harmonic distortion (THD) over a wide line voltage range. The SWS detects the input line root-mean-square (rms) voltage to generate the digital equivalent code to the OTC for optimizing the THD by tuning the on-time value. Besides, the SWS and the OTC provide a feedforward path to reduce the ripple of the feedback voltage for further improving the THD. Therefore, the PFC converter can keep high PF and low THD over a wide line voltage. Experimental results demonstrate the PF is higher than 0.99 and the THD is 1.7% at VACof 90–110V by the test circuit fabricated in TSMC 800V UHV process.

An authentic mode-toggled detector (AMTD) technique is proposed to achieve load and line regulations in a proposed buck-boost (BB) converter. In the case of load transient, conventional BB converter will oscillate and cannot settle to a wellregulated output voltage owing to the on-resistance of the power MOSFETs. Accurate and expeditious mode-toggled detection in the BB converter meet the requirements of load and line transient response by means of the proposed adaptively near-immediate freezer (ANIF) technique. Besides, due to pulse frequency modulation (PFM) implemented in the proposed BB converter, ultra wide load range from 10mA to 900mA can have high efficiency from 80% to 95%. Simulation results show the proposed BB converter fabricated in VIS 0.25μm process can be wellregulated under the input voltage ranging from 2.7V to 4.2V.

The time-shift control (TSC) technique for voltage regulator module (VRM) is proposed to achieve high performance power supply for servers in cloud computing. Four power stages are adopted to provide high current driving capability and low output ripple. Besides, the power request, which includes the number of active phases and voltage identification (VID), is acknowledged by servers for high driving capability during high throughput and high efficiency during standby mode. Furthermore, to equally distribute the current in each phase, the proposed TSC technique improves the current balance performance and solves the stability problem. In the scale-down clouding computing prototype, the efficiency can be kept higher than 90% over a wide load current range of 2 A. Besides, the performance and operating frequency of the servers in stable operation are not limited by the VRM with the TSC.

A self-oscillating constant frequency class-D audio amplifier with voltage control resistor (VCR) technique is proposed for system-on-a-chip (SoC) applications. The VCR control circuit is used to ensure stable switching frequency over a wide range of the modulation index. The proposed method also improves the THD performance at high output power condition. The proposed self-oscillating class-D amplifier can have extremely good performance since the carrier distortion is avoided and the intrinsic harmonic can be attenuated by the second-order loop filter. The VCR control can dynamically adjust the switching frequency according to distinct modulation index. In addition, stable frequency operation can reduce the switching frequency at low output amplitude to improve power efficiency. Experimental results demonstrate that the proposed class-D amplifier can delivers 1.4W to the 8Ω load with a 5V supply. The power efficiency is achieved over 95% and the output THD can be smaller than 0.001%.

A differential-zero-compensator (DZC) technology in constant on-time control dc-dc buck converter which can be applied for the ceramic capacitors is proposed in this paper. Ceramic capacitors are widely used in industry because its low cost. However, the stability often confronts with the sub-harmonic problem related to the incorrect output capacitor and ESR used. In this paper, the proposed DZC technology remits the limitation without adding extra pins and the complexity of circuit still maintain simple. Furthermore, the proposed self-compensated on-time timer (ONT) offers the reliable on-time period with linear solution. In addition, utilizing ceramic capacitor derives smaller ripple of 8mV at 8A. High efficiency of 92.5 % can be guaranteed due to the small ESR value. Stability criteria analysis and simulation results demonstrate that the stability can be ensured even if the ESR is small than 2mΩ.

A high efficiency adaptive frequency hopping (AFH) controlled step-down switch capacitor (SC) DC-DC converter with deep-green mode (DGM) operation is proposed for system-on-chip (SoC) applications. To obtain the high power conversion efficiency and the small output voltage ripple over a wide load current range, the proposed driving capability control can modulate the load current driving with the closed-loop operation. The AFH control can dynamically adjust the switching frequency according to the distinct output load conditions, so as to ensure adequate load current supply function as well as output voltage regulation. In addition, the DGM operation can mask the switching clock to reduce power loss at ultra light loads for improving power efficiency. This work is implemented by 40 nm CMOS technology. Simulated results demonstrate that the propped SC converter delivers wide load range from 1mA to 300mA. The power conversion efficiency is achieved over 72 % and the output voltage ripple is guaranteed smaller than 30 mV.

the current-mode Buck-Boost (BB) converter with the proposed dynamic sawtooth compensation (DSC) technique is able to improve transient response and system stability. To prevent the system switches between buck and boost operations once input and output are nearly equivalent, self-tuning mode selection (SMS) is proposed to decrease output ripple and redundant power consumption by eliminating the mode misjudgment. The duty cycle is decided by the output of error amplifier and sawtooth signal, which can be adequately adjusted to ensure small output ripple and thus to improve efficiency. Besides, the DSC and SMS technique can reduce the inductor current level and the numbers of switching to decrease switching and conduction losses for high efficiency. The converter with the switching frequency of 1MHz was fabricated in 1P3M 0.25-µm CMOS process. The input voltage is in the range of 2.7V to 4.8V for battery-powered devices. The efficiency is higher than 88% when load ranges from 100mA to 400mA.

Reliability of the Power Factor Correction (PFC) system was improved by fast transient response using the proposed triple loop modulation (TLM). Low bandwidth of less than 20 Hz that rejects AC source of 60/120 Hz coupling deteriorated system reliability in case of output load variation. The proposed TLM can automatically adjust bandwidth to rapidly increase or decrease inductor current in order to shorten transient response time. In steady state, system stability can be guaranteed by low-frequency compensation pole without being affected by TLM. The test circuit fabricated in VIS 500 V UHV LDMOS process demonstrated the performance of the highly-integrated PFC controller with the proposed TLM. Experimental results showed that the PFC system with TLM has high PF of 99%, high efficiency of 95%, and high power driving capability of about 90 W. The improvement in transient response is twofold faster than conventional PFC design with output load variation from 90W to 45 W and vice versa.

An additional high-voltage pad is generally applied for one-time-programming (OTP) memory product applications. This may increase the complexity of input/output (I/O) pad arrangement and the area penalty. In this paper, a novel approach of I/O circuit embedded with the power-switch function is proposed for multifunction integrations in one I/O pad. The capabilities of high-voltage programming, I/O signal handling, electrostatic discharge protection and latch-up prevention for this novel circuit are well examined from silicon verifications.

This paper proposes a fast transient (FT) control with the adaptive phase margin (APM) to achieve good transient response in current-mode DC-DC buck converters at different load conditions. The overshoot/undershoot voltage and the transient recovery time are effectively reduced. The APM control can always maintain the system phase margin at an adequate value under different load conditions. That is, the compensation pole-zero pair is adapted to load current to extend the system bandwidth and get an adequate phase margin. Experimental results show the overshoot/undershoot voltage is smaller than 60 mV (3%) and transient period is smaller than 12 μs as load current suddenly changes from 100 to 500 mA, or vice versa. Compared with conventional designs without any fast transient technique, the undershoot voltage and recovery time are enhanced by 45% and 85%, respectively.

A single controller current balance (SCCB) technique is proposed to achieve the time-multiplexing current balance in voltage-mode multi-phase DC-DC buck converter with only one modulation controller. Thus, the N-I controllers can be removed when the SCCB technique is implemented in the monolithic N- phase DC-DC buck converters for largely decreasing the silicon area and power consumption. In addition, the time-multiplexing current balance scheme can further enhance the current sharing accuracy since the mismatches between different controllers does not exist. Simulated results show that the current difference between each phase can be decreased by over 80 % at both heavy load and light load conditions.

The proposed constant on-time control DC-DC converter removes the need of conventional equivalent series resistor (ESR) compensation and simultaneously aims to eliminate equivalent series inductor (ESL) effect of the output capacitor. Since the on-time period is set simply by input and output voltages, the switching frequency in continuous conduction mode (CCM) operation is relatively constant over a wide input voltage range. In addition, fast transient response and small transient dip voltage can be achieved. Simulation results show that the output ripple and the recovery time keep smaller than 5 mV and 10 μs, respectively, when load current step is 500 mA and ESR is smaller than 5 mΩ.

The proposed current-mode synthetic control (CSC) technique in the design of boost converters can improve the transient response time and maintain high conversion efficiency over a wide load range. The CSC technique has high accuracy similar to the current-mode control and doesn't need the slope compensation for simplicity. Besides, the transient response is also improved due to the current-mode hysteresis control. The load- dependent switching frequency at light loads results in high power conversion efficiency. Experimental results show that the output voltage ripple can be kept smaller than 50mV over a wide load current range from 0mA to 400mA with power conversion efficiency higher than 90% at load current of 10mA.

The Avalanche Photodiodes (APDs) are widely used in a variety of optical application requiring high sensitivity, such as long-distance optical communication and optical distance measurement, because the APDs can detect the low level light. APDs accompanied with the Transimpedance Amplifier (TIA) are utilized on the receiver side in the communication system. The trend of integrating the active optical components faces the challenge of integrating different voltage levels. In general, the operation voltage of TIA is usually 1.8 V or 3.3 V. However, the APD requires a high reverse-biasing voltage of 40 V 80 V. Therefore, a high conversation-ratio boost converter must be included to provide the high voltage to bias the APD. Besides, output voltage ripple must be minimized to decrease the influence on communication signals. Experimental results show the 80 V output voltage boosted from the input voltage of 2.5 V. The output voltage ripple is 2 mV under the condition of 1 mA load current.

This paper presented a battery-free energy harvesting system with an auto-startup mechanism to achieve AC power monitoring. The proposed switch capacitor sampler (SCS) technique suppresses the total harmonic distortion (THD) since the energy is derived from the AC power lines. It can improve the performance of the power factor correction (PFC) in the harvesting system to achieve high power utilization. As a result, the proposed method can be used as a smart meter for monitoring or controlling the power delivery decision. A battery-free energy harvesting system with the SCS control technique was implemented by using 0.25-µm CMOS process. The die area is 0.25 mm2. The PF value can be raised to 0.98 with low THD of 17%.

An ultra low-power, precise voltage reference using a switched-capacitor technique in 0.35-μm CMOS is presented in this paper. The temperature dependence of the carrier mobility and channel length modulation effect can be effectively minimized by using 3.3 and 5 V N-type transistors to operate in the saturation and subthreshold regions, respectively. In place of resistors, a precise reference voltage with flexible trimming capability is achieved by using capacitors. When the supply voltage is 1 V and the temperature is 80°C, the supply current is 250 nA. The line sensitivity is 0.76%/V; the PSRR is -41 dB at 100 Hz and -17 dB at 10 MHz. Moreover, the occupied die area is 0.049 mm2.

The fast boost DC-DC converter designed with adaptive voltage positioning (AVP) technique to minimized the right-half plane zero effect is proposed. The concept of constant output impedance is a universal design principle in former works with AVP design. However, the right-half plane (RHP) zero appear in control to output transfer function of boost converter obstruct achievement of constant output impedance. The AC adjusting skill proposed in this paper illustrates how to obtain relative constant output impedance and accomplish the AVP characteristic in boost converter. The boost converter design with the AVP technique provides much faster response time and smaller voltage overshoots or undershoots during the load transient compared with any control scheme presented before. The simulation results is presented to show excellent performance of faster than 4μs response time and the 40mV voltage drop when the load current changes from 100mA to 400mA.

The design of a compact size switching converter under high switching operation causes a drastically decreasing in power conversion efficiency. This paper presents a dual modulation technique to improve the power conversion efficiency with a little increase in output ripple. Especially, the trade-off between the output ripple and the efficiency can meet the requirement of the portable devices. Simulation results show that the converter can operate at 5 MHz with a supply voltage from 3V to 4.5V. The output voltage ripple can be kept smaller than 30mV when load current varies from 20mA to 800mA. Besides, the power efficiency is higher than 85% over a wide load current range.

A load dependent zero-current detector is proposed in this paper for speeding up the transient response when load current changes from heavy to light loads. The fast transient control signal determines how long the reversed inductor current according to sudden load variations. At the beginning of load variation from heavy to light loads, the sensed voltage compared with higher voltage to discharge the overshoot output voltage for achieving fast transient response. Besides, for an adaptive reversed current period, the fast transient mechanism is turned off since the output voltage is rapidly regulated back to the acceptable level. Simulation results demonstrate that the ZCD circuit permits the reverse current flowing back into n-type power MOSFET at the beginning of load variations. The settling time is decreased to about 35μs when load current suddenly changes from 500mA to10mA.

A trade-off performance between static error and dynamic response is made by the combination of proportional (P) and proportional derivative (PD) compensations. Owing to the fast transient response provided by the P compensator, the static error is also reduced by the PD compensator within a reasonable response time. The proposed control circuit is entirely implemented by voltage mode and has better line and load regulations. An asynchronous 1.8MHz DC/DC boost converter was fabricated by UMC 0.35μm to generate 35V output voltage to turn on more than 10 LED at the same time for the notebook’s backlight.

A programmable voltage-to-current converter with linear voltage control resistor (VCR) is presented in this paper. It uses a cascoded flipped voltage follower (CASFVF) to be the input stage in order to enhance the response time and accuracy. Programmability is achieved by using the control signal Vctrlto adjust the equivalent resistance of VCR. Simulation results in 0.25-μm CMOS technology demonstrate the high linearity of the proposed voltage-to-current converter and VCR circuit.

a programmable dual hysteretic window comparator is presented in this paper. The comparator uses a cascoded flipped voltage follower (CASFVF), a high speed VI converter, and a current comparator to enhance the response time and accuracy. Moreover, the positive and negative hysteretic thresholds can be programmable, respectively. Simulation results in 0.25-μm CMOS technology demonstrate the validity of the designed approach.

A load dependent proportional-integration (PI) compensation is proposed in this paper for minimizing transient dropout voltage and accelerating the transient response of current mode DC-DC converters. The adaptive compensation resistance and capacitance are used to react to the sudden load variations: At the beginning of load transient response, the adaptive compensation capacitance is decreased to move the compensation pole-zero pair to a higher frequency for achieving fast transient response. At the end of load transient response, the pole-zero pair is moved back to an optimal position for extending the system bandwidth and phase margin based on the instant load condition. Simulation results demonstrate the excellent performance at transient period and steady-state with this proposed fast transient control and adaptive pole-zero compensation. The overshoot/undershoot voltage is smaller than 45mV and transient period is shorter than 15us as load current suddenly changes between 100mA and 500mA.

A novel dynamic droop scaling (DDS) technique is proposed to improve current sharing performance of multiple supplies system. Owing to the implementation dual current sensing loops, the power dissipation of sensing resistor can be reduced compared with conventional droop technique. Besides, the dual current sensing loops not only increase droop slope but also eliminate the requirement of expensive and accurate external components. Furthermore, the proposed incremental output voltage circuit can raise output voltage to meet the requirement of allowable minimum output voltage according to increment of load current. It means that the DDS can break through the limitation of conventional droop technique. A system supplied by two supply modules with rated 20A output current demonstrates the correction of our DDS technique. The current difference between two supply modules can be shrunk from 12.5A to 2.9A. In other words, the error percentage of current sharing performance can be improved from 42.5% to 8.2%.

A novel feed-forward pulse width modulation (FF-PWM) technique is proposed for improving line regulation of buck or boost (BOB) converters. In order to provide a regulated supply voltage for portable devices, DC-DC converters should have a good line regulation whenever the voltage of the battery is higher or lower than the system supply voltage. Because of the consideration of cost and footprint area issues, we provide a novel BOB converter with FF-PWM, which can provide a regulated supply voltage without the use of transformers or voltage inversion. According to the value of input signals, BOB converters are also useful for dynamic voltage scaling systems or the radio frequency (RF) power amplifier (PA) because it can supply a dynamic voltage suitable for minimum power dissipation. Simulation results show the good line regulation of BOB converters due to the implementation of feed-forward pulse width modulation.

Dithering skip mode with a novel load sensor for DC-DC converters is proposed to maintain a high efficiency over a wide load range. Due to the efficiency drop of the transition from the pulse-width modulation (PWM) to pulse-frequency modulation (PFM), a novel dithering skip modulation (DSM) is introduced to smooth the efficiency curve. Importantly, DSM mode can dynamically skip the number of gate driving pulses, which is inverse proportional to load current. Besides, a novel proposed load sensor can automatically select the optimum modulation method from these three modulation methods without an external selection pin. Simulation results shows DSM can maintain the efficiency of converters as high as about 89% over a wide load current range from 3mA to 500mA.