The increasing complexity of safety-critical hardware systems demands advanced methods for ensuring functional safety (FuSa). Traditional techniques like ATPG and BIST are intrusive, requiring additional hardware and disrupting operations, making them unsuitable for in-field testing. To address this, for the first time, we propose a machine learning (ML)-driven automated Self-Test Library (STL) generation for seamless in-field testing during idle periods, ensuring uninterrupted fault detection and high system performance. Utilizing reinforcement learning, the STL generates design-specific test patterns, achieving up to $57.57 \%$ improvement in fault coverage and up to $85 \%$ efficiency compared to existing pattern-based testing, enhancing FuSa in mission-critical applications.

Small defects and excessive process variability can cause circuit delay changes and result in subtle failures. Such failures, if undetected, can escape to the field resulting in Silent Data Errors (SDE). To expose such failures, we discuss five fault models and the associated scan tests. Of these five, we introduce two new fault models. Silicon results on the E-core of a recent cloud server microprocessor product are described and the relative merits of such tests are determined.

Advancements in integrated circuit manufacturing technology and design complexity have been accompanied by challenges in efficiently ensuring product quality. Aggressive product usage scenarios in critical market segments, such as data centers and automotive, necessitate management of products throughout their lifetime ensuring graceful degradation and replacement. In this session, our first two presenters will discuss defect diagnosis methodologies to enhance product yield and manufacturing quality, while the final presenter will discuss methods to track and address in-field issues.

Integration of analog and RF circuits with advanced node digital systems has leapfrogged analog circuits by several technology nodes. This has resulted in higher defect rates as well as higher process variations. Another point of pressure is that some application domains, such as the automotive industry, require very low defect rates. To ensure that the circuits are thoroughly tested without increasing the test cost severely, test optimization methods can be applied. Examples of test optimization can include the use of alternate tests, reduced test sets, and built-in self-tests. Defect coverage of the optimized tests needs to be evaluated to ensure high-quality products. For analog circuits, defect definitions are generally continuous and minimum detectable deviation (of hard and soft defects) may differ from one test to another. Finding this detectability point is important to compare potential test conditions. In this paper, we propose an algorithm to determine the minimum detectable defect severity for each defect under given test conditions. Ultimately, this information can be used to find the most sensitive test method that already covers the detection limit of other methods. Experiments on an 8-bit ADC circuit show that the proposed algorithm finds the defect detectability limits of different test methods in only a few search steps and yields accurate results.

The increasing complexity of Electrical and Electronic (E/E) systems underscores the need for protective measures to ensure functional safety (FuSa) in high-assurance environments. This entails the identification and fortification of vulnerable nodes to enhance system reliability during mission-critical scenarios. Traditionally, the assessment of E/E system reliability has relied on fault injection (FI) techniques and simulations. However, FI faces challenges in coping with escalating design complexity, including resource demands and timing overheads. Furthermore, it falls short in identifying critical components that may lead to functional failures. To address these challenges, we propose a Machine Learning (ML)-based framework for predicting critical nodes in hardware designs. The process begins with constructing a graph from the design netlist, forming the foundation for training a Graph Convolutional Network (GCN). The GCN model utilizes graph node attributes, node labels, and edge connections to learn and predict critical nodes in the circuit. The model furnishes up to 93.7% accuracy in identifying vulnerable circuit nodes during evaluation on diverse designs such as Synchronous Dynamic Random Access Memory (SDRAM) controller, OpenRISC 1200 (OR1200) modules. Furthermore, we incorporate an explainability analysis to interpret individual node predictions. This analysis discerns the critical design factors influencing fault criticality in the design. Moreover, to the best of our knowledge, we, for the first time, perform a regression analysis to generate node criticality scores, quantifying the degrees of criticality, that can enable prioritizing resources towards critical nodes.

Process variability effects and subtle defect mechanisms in deeply scaled analog/mixed-signal/RF (AMS) silicon technologies combine in malicious ways to increase DPPMs of mixed-signal Systems-on-Chips (SoCs). This has driven the need to increase defect coverage while minimizing testing costs. However, testing embedded AMS components in mixed-signal SoCs has always been a challenge due to test access limitations and requirement for labeled data. In this work, we focus on eliminating the requirement for labeled data. As such, rather than measuring the specification values of embedded AMS components, it is more expedient to devise tests using on- chip resources along with low cost mechanisms for identifying outlier behaviors in measured data to identify devices with parametric and catastrophic defects. To resolve this, what is needed are : (a) a test generation methodology that separates outlier from inlier device behaviors making them easily detectable and (b) a response analysis approach that can draw boundaries between multi-dimensional "good" and "outlier" behaviors with such computational ease that it can be invoked in each test generation iteration to quantify the quality of the test being considered. In this context, a novel test stimulus generation approach using clustering of test data in hyperdimensional spaces is developed that maximizes the similarities of inlier devices in the hyperdimensional space thereby allowing outlier devices to be identified easily by their corresponding hypervector representations from their dissimilarity with hypervectors of inlier devices. Such an approach overcomes the major drawback of prior approaches by eliminating the requirement for labeled data. For decision-making, a one-class hyperdimensional classifier that relies on a single cluster boundary (as opposed to complex boundaries in nonlinear spaces), is used to separate "good" vs. "bad" devices. The classifier is computationally efficient, outperforms existing techniques for defect coverage, and drives the search for the optimal test stimulus. Simulation results on test circuits prove the benefits of the proposed approach over prior testing methods.

Screening for frequency-dependent failures that comprise a significant proportion of Silent Data Errors (SDE) in microprocessors is addressed using timing-aware scan tests. Silicon experiments targeting SDE-sensitive modules in the Core of a recent data center product is performed using such tests. Vmin measurements with these tests demonstrate the promise of this approach.

Integrating analog circuits with the most advanced digitally-tuned processes increases the defect rates and the risk of in-field wear out. Coupled with the reduced accessibility arising from this level of integration, increasing defect rates necessitate systematic approaches to analog testing. Structural built-in self-test (BIST) for analog circuits can reduce test development complexity. In this paper, we propose a robust and low-cost structural BIST method for analog circuits. The proposed method relies on perturbing the analog circuit at an injection point and observing the result at an observation point as a digitally measurable time delay. Injection can be achieved via simple ON/OFF keying while the observation can be achieved by a self-referencing comparator. Multiple injection points can be selected at low cost (single transistor) while the observation circuit can be shared across many injection points and across different circuit blocks. The proposed method is demonstrated on two circuits, showing that 96% of catastrophic faults can be detected with the proposed approach with six injection points.

Low-level hardware faults manifested in a Deep learning (DL) accelerator usher in graceless degradation of high-level classification accuracy, which can eventuate to catastrophic circumstances. This violates the crucial Functional Safety (FuSa) of the DL accelerator, maintaining which is imperative in high-assurance applications. Conventional techniques for error localization incur high-test efforts, without regards to the unique challenges posed by DL systems. In this direction, we propose DiagNNose, a two-tier machine learning-based error localization framework for on-line fault management in DL accelerators. We develop a novel diagnostic pattern selection algorithm to obtain a minimal subset of functional test patterns, that are executed in the accelerator in mission mode. By extracting and analyzing dataflow-based features from the intermediate computations of the general matrix multiply (GEMM) core, a lightweight multilayer perceptron accomplishes bit-level error localization in 8-bit, 16-bit, and 32-bit datapath units with high fidelity. We have limited ourselves to a single accelerator design, i.e., the versatile tensor accelerator (VTA) architecture to evaluate our proposed DiagNNose framework. On executing state-of-the-art deep neural networks trained on ImageNet; error localization using only 30 diagnostic functional test patterns demonstrate up to 98.4% diagnosability, thereby demonstrating an improvement of 54.63% over a random test pattern set, with as low as 4.95% overhead in the DL accelerator in mission mode.

The extensive adoption of safety-critical applications in high-assurance environments, such as the automotive domain, has laid emphasis on safeguarding the reliability and Functional Safety (FuSa) of the Electrical and/or Electronic (E/E) components constituting such systems. Most modern automotive Systems-on-Chips (SoCs) comprise Analog and Mixed Signal (AMS) circuits, which are more susceptible to faults than their digital equivalents. However, their attributes of operating in the continuous signal region can be leveraged to perform early anomaly detection, which could facilitate the subversion of the eventual hardware failure state, thereby improving the FuSa of the system. To this end, we had proposed a novel unsupervised learning-based early anomaly detection framework catered to automotive AMS circuits (in ITC 2022). However, existing approaches to AMS FuSa violation detection are limited by pre-specified feature inputs, and lack rationale for identifying signals to be monitored to perform anomaly detection. To address these issues as well as further augment our original solution, in this paper, we propose a novel anomaly detection strategy that involves: (1) a genetic algorithm-based feature selection approach, (2) a novel signal selection algorithm that ascertains the best intermediate circuit signal, for furnishing enhanced anomaly detection accuracy, while reducing the associated detection latency, and (3) an explainable AI (XAI)-based framework that boosts user interpretability and transparency of the anomaly detection framework. This XAI approach, in turn, can be provided as feedback to the designer during circuit design and validation. The proposed approach is evaluated using case studies of two representative AMS circuits, which are prevalent in automotive SoCs. Our experimental analyses demonstrate that the proposed approach furnishes up to 100% detection accuracy and 2.3× reduction in detection time compared to our existing framework, in addition to providing insights by improving transparency of the anomaly detection framework, thereby exhibiting the efficacy of our solution.

The proliferation of Deep Neural Networks (DNNs) in real-time mission critical applications has promoted the implementation of custom-built DNN inference accelerators. These accelerators require a considerable amount of on-chip memory to store millions of trained DNN parameters for executing inference at the edge. Drastic technology scaling in recent years have made these memory circuits highly vulnerable to faults due to various reasons like aging, latent defects, single event upsets, etc. Such faults are highly detrimental to the classification accuracy of the DNN accelerator, leading to the crucial Functional Safety (FuSa) violation. This can eventuate to catastrophic circumstances, when used in mission-critical applications. In order to detect such violations in mission mode, we propose to generate a set of functional test patterns by leveraging the concept of Generative Adversarial Networks (GANs), that are independent of the DNN model and the accelerator characteristics. Our experimental results demonstrate that, the generated test patterns significantly improve FuSa violation detection coverage by up to 130.28%, compared to existing techniques. To the best of our knowledge, this is the first work that generates GAN-based test patterns in order to perform FuSa violation detection in mission-critical DNN accelerators.

The proliferation of deep learning algorithms has catalyzed their utilization to solve a multitude of real-world problems. Algorithms such as deep neural networks (DNNs) are compute- and power-intensive, thereby accentuating the development of hardware platforms like DNN inference accelerators. However, inference execution of large DNNs in resource-constrained environments induces energy bottlenecks in these accelerators. Since large DNNs consist of hundreds of millions of trained parameters, accessing them from the accelerator memory incurs substantial energy. To address this challenge, we propose HardCompress, which, to the best of our knowledge, is the first low-power solution that uses traditional compression strategies pertaining to commercial DNN accelerators in resource-constrained IoT edge devices. The three-step approach involves hardware-based post-quantization trimming of weights, followed by their dictionary-based compression and subsequent decompression by a low-power hardware engine during inference in the accelerator. We evaluate the proposed solution on lightweight networks trained on the MNIST dataset, the compact model trained on the CIFAR-10 dataset, and large DNNs trained on the ImageNet dataset. Performance of HardCompress at different quantization levels has been analyzed. Furthermore, to quantify the effectiveness of the proposed solution, an energy framework that contrasts the DRAM energies of the original and HardCompressed models has been developed. Finally, a fault injection framework which compares the fault resilience of the original model with its HardCompressed counterpart is also proposed. Our results exhibit that HardCompress, without any performance degradation in large DNNs, furnishes a maximum compression of 99.27%, equivalent to$137\times $reduction in memory footprint and 0.07 J for 8-bit quantization in the systolic array-based DNN accelerator. Furthermore, our proposed low-power decompression engine incurs an area overhead of only 0.02%; thus, enabling HardCompress’ utilization in resource-constrained environments.

A logic diagnosis procedure produces a set of can-didate faults that are expected to identify the defects present in a faulty chip. To reduce the number of candidates produced, diagnostic tests are often needed. The use of diagnostic tests increases the storage requirements of a test set. Earlier works reduced the input storage requirements of a fault detection test set by using each stored test to apply several different tests. When applied to diagnostic tests, the tests were selected by performing diagnostic fault simulation of a basic fault model. In this paper, we apply this approach to target large sets of candidate faults produced by a logic diagnosis tool. A procedure for the selection of a subset of the available tests to be used as diagnostic tests is described. Experimental results for simulated defects in benchmark circuits and the logic blocks of an OpenSPARC T1 microprocessor show that the diagnostic test set selected using our approach produces better diagnosis results, with a minimal increase in input storage, compared to a diagnostic test set produced by a commercial tool.

In the latest technology nodes, there is a growing concern about yield loss due to timing failures and delay degradation resulting from manufacturing complexities. Largely, these process imperfections are fixed using empirical methods such as layout guidelines and process fixes which come late during the design cycle. In this work, we propose a framework for improving the design yield by synthesizing netlists with improved ability to withstand delay variations to reduce yield loss. We advocate a defect tolerant approach during early design stages to synthesize netlists by introducing defect-awareness to EDA synthesis, thereby generating robust netlists that can withstand delays induced by process imperfections. Toward this objective, we present a) a methodology to characterize standard library cells for delay defects to model the robustness of the cell delays, and b) a solution to drive design synthesis using the intelligence from the cell characterization to achieve design robustness to timing errors. We also introduce defect tolerance metrics to quantify the robustness of standard cells to timing variations, which we use to generate defect-aware libraries to guide defect-aware synthesis. Effectiveness of the proposed defect-aware methodology is evaluated on a set of benchmarks implemented in GF 12nm technology using static timing analysis (STA), revealing a 70--80% reduction of yield loss due to timing errors arising from manufacturing defects, with minimum impact on the area, power and no impact on performance.

During manufacturing of integrated circuits, it is imperative for cost and quality that defects that occur on die are screened early in the test process, preferably before packaging. As part of screening, stress steps are performed to accelerate latent defects so that they become observable and are detected by subsequent test steps. Traditionally, the levers for applying stress have been increased supply voltage and temperature while concurrently running a sliver of content that had been created to “test” defects. In this paper, we describe a methodology to generate content specifically targeting stress at latent defects by maximizing electrical activity. Our goal is to efficiently accelerate all classes of latent defects. This paper will give details of the technology and content generation methodology for scanned digital logic. Silicon results are provided on a recent client product. Ongoing work that extends this to address latent defects in other areas of the die are outlined.

Achieving high yield in deep-submicron technologies is challenging due to the presence of unforeseen defect mechanisms, requiring increases in test complexity and efficiency. We focus on shorts within standard cells which are traditionally targeted by DC tests. Recent research has shown the need for multi-pattern tests where intermediate defect resistance values are concerned, as opposed to extreme values considered by prevalent test techniques. In this research, we show that there exist ranges of short defect resistance values that escape traditional DC tests while incurring unexpectedly large delay values for specific two-pattern stimuli. It is seen that these resistance values are approximately in the range of defect resistance values observed for realistic short defects in industry. These defects must therefore be prioritized from a circuit level critical path delay testing perspective to minimize overall circuit DPPM. Such catastrophic increase in delay is due to the fact that specific shorts in standard cells influence the delays of logic gates feeding into and out of the standard cell, resulting in path delay increase of 50X-SOX with respect to the delay of a single cell. Two-pattern tests are derived for such faults and simulation results on standard cell designs and ripple carry adders are presented to further our arguments.

High accuracy and ever-increasing computing power have made deep neural networks (DNNs) the algorithm of choice for various machine learning, computer vision, and image processing applications across the computing spectrum. To this end, Google developed the tensor processing unit (TPU) to accelerate the computationally intensive matrix multiplication operation of a DNN on its systolic array architecture. Faults manifested in the datapath of such a systolic array due to latent manufacturing defects or single-event effects may lead to functional safety (FuSa) violation. Although DNNs are known to resist minor perturbations with their inherent fault-tolerant characteristics, we show that the classification accuracy of the model plummets from 97.4% to 7.75% with a minimal fault rate of 0.0003% in the accelerator, implying catastrophic circumstances when deployed across mission-critical systems. Hence, to ensure FuSa of such accelerators, this article provides an extensive FuSa assessment of the accelerator exposed to faults in the datapath, by varying the network parameters, position, and characteristics of the induced error across multiple exhaustive data sets. Furthermore, we propose two novel strategies to obtain a diminutive set of functional test patterns to detect FuSa violation in a DNN accelerator. Our experimental results demonstrate that the obtained test sets can achieve an average of 92.63% (in some cases, up to 100%) fault coverage with cardinality as low as 0.1% of the entire test data set.

Recent advances in process technology have resulted in novel defect mechanisms making the test generation process very challenging. In addition to complete opens and shorts that can be represented via extreme defect resistance magnitudes, partial resistive opens and shorts are also of concern in deeply scaled CMOS technologies. For open defects with intermediate defect magnitude values, it has been shown that multi-pattern tests are necessary for defect exposure. We extend this approach to short defects with intermediate defect magnitude values to obtain a suite of multi-pattern tests for standard cell instances that cover complete as well as partial intra-cell open and short defects. A hierarchical scan-compatible SAT-based test generation approach for full scan sequential circuits is then proposed that allows such multi-pattern tests to be applied to the circuit via the scan infrastructure. A key innovation is the combined use of shift and capture operations along with launch-on-capture and launch-on-shift scan based test application for increased defect coverage. Resulting defect coverage improvements over conventional two-pattern tests are demonstrated on ISCAS89 benchmark circuits.

We propose a framework to co-optimize Yield along with Power, Performance and Area (PPA) through the design flow from logic synthesis through placement and routing (APR). We accomplish this by learning from silicon using a combination of test/diagnosis, inline/metrology and Failure Analysis (FA) results to create predictive models using Machine Learning (ML) techniques that are then used during design. Simulation results across three different CPU and Graphics cores show promising results with projected yield improvements of 11-17% with no area and performance / timing penalty with respect to design targets but with tradeoffs to both static and dynamic power. Better joint exploration of the PPA space along with yield indicates it is possible to recover yield with close to iso-PPA with respect to design targets. Pre-silicon results show ~10.4% yield increase with iso-area and -iso-performance and ~1% power penalty on a processor core.

We advocate defect tolerant design to improve timing yield. A metric of defect tolerance is proposed, and an approach based on using defect tolerance metrics, derived for each cell in a library, to bias logic synthesis and automated placement and routing (APR) to achieve netlist-level defect tolerance is explored. We compare our proposed approach, in which the delays of cells are penalized in accordance with their defect vulnerability to two alternative approaches: 1) an approach in which the most defect vulnerable cells are removed from consideration during automated design, and 2) another that gains yield by frequency-push over-design. We measure timing yield based on modeling defects as cell delay increments and using static timing analysis to evaluate the various approaches. Simulation results show promising timing yield improvements, with one case showing about 9.5% timing yield increase with under 3% area and 2% power costs.

Ensuring high defect coverage for advanced CMOS technology nodes has been a major challenge for the IC test industry. Traditional test methods using fault models such as stuck-at and transition faults with a primitive gate-level abstraction of design netlists have been shown to be inadequate for detecting open-circuit and short-circuit defects within instances of standard cells used in those netlists. Recent advances in Cell-Aware Test (CAT) using single pattern and two pattern tests have demonstrated increased coverage of such defects in industrial IC designs. However, the simulation overhead of defect characterization for all the cells in a library practically limits the size of defects that are explored to large magnitudes. Furthermore, certain effects such as charge sharing within cells can necessitate tests that span more than two time frames to expose subtle defects. This work, through simulation, identifies defects of certain sizes that can go undetected by current methods. It then proposes an algorithmic approach towards cell characterization that can result in faster identification of cell input stimuli vis-a-vis a defect simulation based method.

Start of the above-titled section of the conference proceedings record.

Start of the above-titled section of the conference proceedings record.

We introduce a methodology for automated test compression during electrical stress testing of analog and mixed signal circuits. This methodology optimally extracts only portions of a functional test that electrically stress the nets and devices of an analog circuit. We model test compression as a problem of optimizing functional of the transient response. We present a random tree based approach to find optimal solutions for these computationally hard integrals. We demonstrate with an op-amp, VCO and CMOS inverter that the method consistently reduces the length of each test by an average of 93%.

A practical fault simulation methodology for analog circuits in mixed-signal designs is presented. The methodology leverages the mixed-signal simulation environment of a product and performs mixed-signal fault simulation of embedded analog circuits. A set of open-circuit and short-circuit faults are extracted with guidance from layout parasitics, and automatically injected in to the net list. Fault coverage of manufacturing tests on faults in the transmitter of a high speed serial interface design are reported with two different observation criteria. Results indicate the amount of test reduction that can be achieved and the importance of appropriate observation in fault detection.

A new methodology for extracting compact test stimuli from functional tests for infant mortality testing of analog circuits is proposed. The test stimuli are extracted such that they produce extremal electrical activity in the circuit to push latent defects over the edge to become hard defects. Results on analog modules from the receiver sub-system of a high speed serial interface show that tests that are about 1/5th the size of the original functional test can be extracted while achieving consistently at least 80% of the electrical activity of the functional test.

Summary form only given. Modern IC design and manufacturing have progressed in leaps and bounds, resulting in unimaginable integration, and power-performance advancements. This progress has been accompanied by adverse design-layout-process interactions and increased defect sensitivity. Controlling these complex interactions has exacted a steep price in terms of delaying yield ramp, extending silicon validation to characterize and fix marginal effects, and test screening being overwhelmed in time and volume to be able to ensure outgoing customer quality. There is, however, a bright side. Each step of the manufacturing, validation and test process generates information. This information, if effectively organized and analyzed, has the potential to result in efficiency and quality improvements that parallel in scale to the manufacturing process itself. Recent developments in data analytics methods have enabled harnessing of this information towards some benefits, while promising much more. This panel will explore major problems that can potentially be solved with advanced analytics, and also current solutions in the market targeted at some of these problems. Experts from integrated and fabless design houses will present their perspective on problems they encounter, while vendors of EDA solutions on data analytics will shed light on the nature of problems solved by current methods and those that will be addressed by solutions to come.

There has been a significant interest in Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) as a candidate for emerging memory technology for last-level embedded caches in the recent years. High density (3-4x of SRAM), non-volatility, nano-second Read and Write speeds, and process and voltage compatibility with CMOS are the attractive properties of this technology. A few studies have expounded on the reliability in this technology but various fault manifestations have not been studied in detail in the past. This paper attempts to study the fault models in STT-MRAM under both parametric variations as well as electrical defects (opens and shorts). Sensitivity of Read, Write and Retention to material and lithographic process parameters has been studied. Also electrical defects viz. intra-cell and inter-cell opens and shorts have been considered and the corresponding fault models have been identified and classified.

The era of Internet-Of-Things, or IOT - ubiquitous connected components, shared across an intelligent communication medium, and analyzed by massive storage and analysis “clouds” - has begun. With development of deep integration and sensor technologies, very high speed network connectivity, and huge server farms that can provide 24×7 service, the ability to monitor, process and optimize our work and personal life is at our door step.

The traditional focus of work in test has been innovation and efficiency for high volume manufacturing test. However, in reality, a significant amount of effort is expended on design validation and debug prior to deeming analog and high speed serial IO test stimuli content production worthy. In this presentation we emphasize the importance of widening the post-silicon envelope to include early design validation and debug in addition to manufacturing test. The impact on DFX architecture is considered in which in order to be efficient the architecture has to be scalable across a wider set of post-silicon stages. We also discuss the need for establishing quick correlation between design validation and manufacturing test measurements and the time-to-market savings it brings for analog and IO content designed essentially on a digital process technology.

Wafer-level spatial correlation modeling of probetest measurements has been explored in the past as an avenue to test cost and test time reduction. In this work, we first improve the accuracy of a popular Gaussian process-based wafer-level spatial correlation method through two key enhancements: (i) confidence estimation-based progressive sampling, and, (ii) inclusion of spatio-temporal features for inter-wafer trend learning. We then explore a new application of the enhanced correlation modeling method in estimating High Volume Manufacturing (HVM) yield from a small set of early wafers and we demonstrate its effectiveness on a large set of actual industrial test data.

Achieving automotive quality requires IC tests that achieve 100% coverage of potential defects. With new cell-aware digital test pattern generation techniques and the simple stuck-at fault model, this has proven practical for digital circuitry, but there is no equivalent for mixed-signal circuitry. A simple but realistic analog defect model is described, based on industrial observations and theory. It is consistent with previous proposals, but has novel differences that make it suitable for schematic and layout-extracted netlists and more efficient to simulate. A couple of examples show its effectiveness.

Ever larger on-die memory arrays for future processors in CMOS logic technology drive the need for dense and scalable embedded memory alternatives beyond SRAM and eDRAM. Recent advances in nonvolatile spin transfer torque (STT) RAM technology, which stores data by the spin orientation of a soft ferromagnetic material and shows current induced switching, have created interest for its use as embedded memory. STTRAM exhibits scalable write current, sufficient read margin and nonvolatility or persistence, all of which make it an attractive solution for last level cache, embedded cache or even main memory. In an era of on-die non-volatile storage, new defect, disturb and fault mechanisms need to be comprehended during characterization as well as manufacturing tests. The first part of the talk will introduce STTRAM and review the fundamentals of the cell design, the read and write mechanisms as well as recent advances in technology, which make it a potential successor to eDRAM, followed by how variations and thermal noise limit the material and cell design space. The second part will discuss new test models that would be required for such non-volatile storage, the necessity of large scale data collection and analysis, as well as the need for BIST and on-line testing, and conclude with challenges and opportunities in STTRAM testing that lie ahead of us.

Analog circuits embedded in large mixed-signal designs can fail due to unexpected process parameter excursions. To evaluate manufacturing tests in terms of their ability to detect such failures, parametric faults leading to circuit failures should be identified. This paper proposes an iterative sampling method to identify these faults in large-scale analog circuits with a constrained simulation budget. Experiment results on two circuits from a serial IO interface demonstrate the effectiveness of the methodology. The proposed method identifies a significantly larger and diverse set of critical parametric faults compared to a Monte Carlo-based approach for identical computational budget, particularly for cases involving significant process variations.

The rapid pace of integration, emergence of low power, low cost computing elements, and ubiquitous and ever-increasing bandwidth of connectivity have given rise to data center and cloud infrastructures. These infrastructures are beginning to be used on a massive scale across vast geographic boundaries to provide commercial services to businesses such as banking, enterprise computing, online sales, and data mining and processing for targeted marketing to name a few. Such an infrastructure comprises of thousands of compute and storage nodes that are interconnected by massive network fabrics, each of them having their own hardware and firmware stacks, with layers of software stacks for operating systems, network protocols, schedulers and application programs. The scale of such an infrastructure has made possible service that has been unimaginable only a few years ago, but has the downside of severe losses in case of failure. A system of such scale and risk necessitates methods to (a) proactively anticipate and protect against impending failures, (b) efficiently, transparently and quickly detect, diagnose and correct failures in any software or hardware layer, and (c) be able to automatically adapt itself based on prior failures to prevent future occurrences. Addressing the above reliability challenges is inherently different from the traditional reliability techniques. First, there is a great amount of redundant resources available in the cloud from networking to computing and storage nodes, which opens up many reliability approaches by harvesting these available redundancies. Second, due to the large scale of the system, techniques with high overheads, especially in power, are not acceptable. Consequently, cross layer approaches to optimize the availability and power have gained traction recently. This session will address these challenges in maintaining reliable service with solutions across the hardware/software stacks. The currently available commercial data-center and cloud infrastructures will be reviewed and the relative occurrences of different causalities of failures, the level to which they are anticipated and diagnosed in practice, and their impact on the quality of service and infrastructure design will be discussed. A study on real-time analytics to proactively address failures in a private, secure cloud engaged in domain-specific computations, with streaming inputs received from embedded computing platforms (such as airborne image sources, data streams, or sensors) will be presented next. The session concludes with a discussion on the increased relevance of resiliency features built inside individual systems and components (private cloud) and how the macro public cloud absorbs innovations from this realm.

At the 1999 ITC, Pat Gelsinger from Intel delivered an important keynote address where he outlined the need for a low-pin count tester with lower performance pin electronics to meet the stringent test cost requirements of a billion transistor machine. At the 2009 ITC, engineers from AMD came forward with an I/O test solution that is believed to meet the Intel challenge using a cash-resident self-testing strategy combined with an external low-pin count tester. How can we drive major challenges to post-silicon validation and in huge variance era? Technology scaling enables us to trade off amplitude resolution for time resolution. Accordingly, both internal and external tests, some of which use low-pin count testers, are also shifting from voltage centric tests to timing centric tests. How can time resolution be used to push the timing centric tests beyond current limitations? How can spatial resolution be realized to enhance yields in terms of both die-to-die variations and within-die variations? What is necessary to provide robust on-chip solutions subject to huge variations, which may be combined with an external low-pin count tester?

Summary form only given. In the industry today, testing packaged chips achieves the outgoing DPPM (defective parts per million) requirements. Usually, functional and structural test patterns are used at wafer sort, followed by functional/structural testing with packaged parts, and then by functional system level testing, each subsequent stage significantly more expensive than the previous one. By and large, wafer test have not been used for performance binning and reliability screening. Also, packaged parts are tested in burn-in chambers and on load boards, using either the same structural patterns used at wafer sort or with functional test patterns. As design complexity has gone up significantly over the past decade, the test cost has grown disproportionately. If a die is found to be faulty at a stage after wafer sort, then the design house incurs the cost of packaging, and for subsequent testing. In one business model, the fabless design house buys dies from the foundry that pass wafer sort, and needlessly pays for dies that are later found to be bad after packaging. Furthermore, this problem can be severe for dies that go into multi-chip modules or stacked ICs, as all the dies in the packaged chip have to be thrown away even if one constituent die is found to be bad. Since it is increasingly more expensive to test chips down-stream (using functional testers or on a system) and since there is downward pressure on product costs with the advent of inexpensive SoCs, it becomes important to achieve maximum test quality in terms of defectivity and binning, at wafer sort. Known good die (KGD) refers to dies which have been tested to the same quality and reliability levels as their packaged counterparts. Even though the KGD problem has been discussed since the mid 90's, the problem becomes more and more difficult with every new process node and new design requirement. There is need to develop high quality tests, on die DFX instrumentation, and reliability screens that can be applied at wafer sort, given pin constraints. In addition to addressing failure mechanisms of a bare die, such as gross defects, small delay defects, cross-talk, and variations due to photolithography, a good wafer sort test methodology and associated tests should not only be enough to reject bad bare dies, but also characterize the dies enough to enable estimation of the performance/power of packaged parts on a system.

Today's electronic systems and those envisioned for the near future exploit significant integration of devices on a chip with incredibly shrinking device/interconnect geometries. Such systems operate very close to their power/performance margins to achieve maximum profitability. The increase in the design complexity of such systems that now include digital and analog components, coupled with the race to reach the market faster severely constrains the resources and time to validate and test them. Furthermore, products can also fail to operate correctly in the field prior to their expected end-of-life due to transient errors or aging.

Functional test content to screen for electrical marginalities during silicon validation are not generated with the goal of identifying speed-limiting paths, adversely affecting the quality and efficiency of validation. We propose a methodology to generate functional tests to excite pre-silicon timing-critical paths along with environmental effects such as voltage droop. These tests are to replace random/function-targeted content as the source for identifying speed failures during silicon validation. The effectiveness of this methodology is demonstrated through silicon experiments on a recent processor.

Silicon bring-up aims to achieve validation across a desired spread of power and performance for an integrated circuit product such as a microprocessor, and manufacturing test aims to screen out defects and classify parts into a range of performance bins. Both these steps are increasingly becoming complex due to shrinking device dimensions causing circuit performance to become highly sensitive to voltage variations such as high/low frequency voltage droops and IR drop. During bring-up, the sensitivity of performance to voltage behavior is also not consistent and correlated across different validation platforms such as a system (board) or a tester, or across different test methodologies such as functional testing or scan testing. This voltage sensitivity coupled with lack of sufficient silicon observability of voltage behavior in a cycle-by-cycle manner adversely impacts silicon debug efficiency during bring-up both on the system and on the tester. This can lead to sub-optimal fixes in each silicon iteration and increased iterations. This can increase time-to-market, and also significantly reduce yield during manufacturing test. The downward pressure on product cost necessitates that test cost scales proportionally. The high cost of functional test development to achieve a desired coverage, the relatively high functional tester costs vis-à-vis the costs of structural testers, and increased complexity of low-yield analysis and failure analysis (FA) with functional tests due to large number of cycles that need to be simulated to reason about failures, all conspire to render production testing with functional tests increasingly infeasible. To address the need for adequate defect coverage at a desired operating frequency using scan-based tests that is at par with that provided by functional tests, at-speed application of scan tests becomes necessary. Recently published literature has indicated increased voltage sensitivity to at-speed scan test application and increased power dissipation during at-speed test. To avoid yield loss and test escapes due to these issues, it becomes necessary to match or correlate the dynamic voltage and current profiles of scan tests to those of functional tests which have been accepted so far as a de facto standard (though not golden). However, for scan-based testing to replace functional tests effectively, it is imperative that voltage/power profiles during functional tests be characterized adequately. Scan test application schemes and scan test content that can provide voltage/power profiles that match those of functional tests can then be developed to reduce product test cost without compromising quality. This session explores characterization of power delivery network on a silicon die, its impact on silicon bring-up, and on effectiveness of functional and at-speed scan-based manufacturing test.

We present a technique that deals with the problem of efficiently generating instruction sequences to test for delay defects in a processor. These instruction sequences are loaded into the cache of a processor and the processor is run in its normal functional (native) mode to test itself. The methodology that we present avoids the significant increase in search space of a previous method while generating tests. We also present a technique which increases the probability of detecting multiple delay faults with a single instruction sequence. This technique can help immensely in reducing the cost of test. We demonstrate the effectiveness of our technique on an off-the shelf processor.

In this paper, we propose an approach to accelerate path delay fault simulation of long test sequences. Several key ideas, namely judicious selection of path delay faults to be simulated, extraction of a compact set of necessary conditions to detect selected faults at primary inputs, and an on-demand selective simulation of input vectors based on their satisfaction of these necessary conditions, are proposed. We demonstrate the benefits of our methodology via experiments on benchmark circuits, with one large test case (S9234) showing a 114X speed-up over a traditional approach.

Device failure mechanisms of today's deep sub-micron processes are not well-modeled by single stuck-at faults, and hence several advanced fault models have been proposed in the past. Gate-exhaustive fault models were proposed to exercise a gate completely and then observe the resultant response at an observable output. This paper extends the gate-exhaustive fault model to target bigger regions (a collection of gates) with the hypothesis that exercising a region with an exhaustive pattern set can yield coverage on a larger proportion of unmodeled defects. To test out this hypothesis, we use the logic proximity bridge (LPB) fault model as a surrogate for unmodeled defects and grade the region and gate exhaustive patterns against the LPB fault model to gauge their efficacy. We show that region exhaustive patterns are better at detecting untargeted LPB faults compared to patterns obtained using gate exhaustive or traditional stuck-at fault models.

Path delay fault simulation performance on multi-cycle delay paths common in industrial designs is discussed using paths from a large block in a microprocessor and a functional test vector suite. We profile fault simulation performance using a novel multi-cycle path delay fault simulator. Our experiments show that path delay fault simulation run-time grows linearly with path list size. Contrary to commonly held notion that path delay fault simulation is more expensive than stuck-at fault simulation, our experiments show that performance of path delay fault grading is comparable to that of stuck-at fault grading. Finally, we propose and evaluate a heuristic that can improve path delay fault simulation performance and also aid in selection of tests for speed-limiting paths.

The need for high-performance pipelined architectures has resulted in the adoption of latch based designs with multiple, interacting clocks. For such designs, time sharing across latches results in signals which propagate across multiple clock cycles along paths with multiple latches. These paths need to be tested for delay failures to ensure reliability of performance. However, many of these multi-cycle paths can be untestable and significant computational effort is wasted in targeting such paths during test generation and fault grading. To save this computational effort, a-priori identification of untestable multicycle paths is desired. We address this issue in our paper through a novel and unique framework: unlike traditional techniques, which focus only on single-cycle path delay faults (for flip-flop based designs with single clock), our framework efficiently identifies untestable multi-cycle path delay faults (Mpdfs) in latch-based designs with multiple clocks. We use a novel graphical representation and sequential implications to identify non-robustly untestable M-pdfs through a three-step methodology. Results for industrial designs demonstrate the effectiveness and scalability of our framework.

An efficient crosstalk target identification framework called XIDEN has been developed that is used prior to the computationally expensive processes of crosstalk validation and test generation. XIDEN is mainly composed of a set of extractors and filters that together identify the prime crosstalk targets. These prime targets include all error producing targets, i.e. targets that can potentially create Boolean errors. A methodology has been developed to determine the sequence of extractors and filters to identify a small set of targets with low computational cost. The effects of process variation and extraction accuracy as well as complexity are considered in XIDEN. After performing a training process on sample circuits, XIDEN produces a set of effective extractor filter sequences to be used for production circuits.

We address the testing of delay faults in domino circuits that contain complex gates. The different ways in which these faults can cause errors are demonstrated. We identify structures in both the evaluate and the precharge logic that should be tested for delay faults. We propose conditions to generate delay tests for them, and outline extensions to handle mixed static-domino circuits. Testability results are reported for benchmark circuits that are mapped to domino gates and in-house domino circuits.

Gate-level models are usually used to generate tests for circuits containing non-primitive CMOS gates. It is shown that tests generated using these models and classical conditions for robust path delay testing can fail to detect delay faults in such circuits. A new delay-independent, switch-level delay test methodology, called /spl tau/-robust testing, is proposed that defines new entities called targets and proposes conditions to generate tests for each target. It is proven that, under the assumed delay model, a circuit that passes a test set containing a /spl tau/-robust test for every target is guaranteed to operate correctly at the desired speed. The effectiveness of the proposed methodology is demonstrated by (a) illustrating the difference between the delays excited by classical robust and /spl tau/-robust tests via circuit simulation, and (b) generation of /spl tau/-robust tests for benchmark circuits and comparison of /spl tau/-robust coverage of classical robust and /spl tau/-robust test sets.