Numerical simulation is an important tool used in various fields of computational science and engineering. The models to be solved by simulation are predominantly based on equations which require the discretization of a spatial domain. The accuracy of the simulation results is heavily influenced by the properties of the underlying spatial discretization, the mesh. Thus, adapting a mesh to meet certain criteria is an integral step to achieve a desired accuracy and high computational performance. With the trend of more and more cores on a compute node, it is essential to efficiently exploit this available on-node parallelism of modern multi-core systems. Our work introduces a flexible shared-memory parallelized mesh adaptation framework. We show the integrability of available serial mesh adaptation algorithms and applicability to multi-region meshes. The first step of the framework is the partitioning of the initial mesh, where all the resulting partitions are subsequently assigned to independent sets using graph coloring algorithms. These sets are then processed in parallel using two different adaptation algorithms: A template-based algorithm and a Delaunay-based algorithm provided by the TetGen software. We perform benchmarks using a cube geometry with different mesh resolutions as well as a model of a microelectronic transistor device structure to demonstrate the scalability of our approach and investigate the resulting element quality. The obtained speedups for this inherently memory-bound problem and for constant problem sizes range between 4.6 and 8.6 using 16 threads.

The Fast Marching Method is widely used for the solution of the Eikonal equation in problems arising in science and engineering applications. A common application is the calculation of the distance to an interface resulting in a signed distance field. The Fast Marching Method is a non-iterative high accuracy method. However, the sequential nature of the algorithm does not favor a straightforward parallelization. Many parallelization approaches have been presented so far, but they do not provide a reasonable parallel efficiency. Recently, a promising new approach based on an overlapping domain decomposition technique has been introduced, providing a scalable, widely applicable parallel algorithm. However, investigations so far were limited to synthetic point-based problem cases which do not cover the much more challenging cases of interface re-distancing, where instead of simplistic point sets, challenging interface geometries are processed. In this work we fill this gap by analyzing a shared-memory implementation of the parallel Fast Marching Method for three-dimensional interface problems, covering the key challenges and various domain decomposition strategies. The parallel efficiency and run-time performance is examined on a dual-socket Ivy Bridge-EP compute node. Our analyses clearly outline the feasibility limits of a shared-memory parallel Fast Marching Method.

We may soon experience an exhaustion of the economically unlimited growth in the semiconductor industry.

For process and device simulation, very high mesh densities are often required to obtain accurate simulation results. Unfortunately, the required mesh densities depend often on a direction. Conventional mesh-refinement strategies generate isotropic meshes with a high amount of mesh points, reaching the memory and time limits in particular for three-dimensional simulations. For a better resolution of the carrier concentrations, for instance, a boundary-conforming mesh-generation method with tunable mesh spacings in almost orthogonal directions was developed. Similar to elliptic mesh generation, the mesh points are placed inside the simulation regions based on the solution of partial differential equations. The method used can produce highly anisotropic mesh densities in the regions of particular interest. In contrast to elliptic grid generation, which produces structured grids, the method used generates triangular or tetrahedral (unstructured) Delaunay meshes in two or three dimensions, respectively, which are very well suitable for the process and device simulators.

This paper presents an anisotropic adaptation strategy for three-dimensional unstructured tetrahedral meshes, which allows us to produce thin mostly anisotropic layers at the outside margin, i.e., the skin of an arbitrary meshed simulation domain. An essential task for any modern algorithm in the finite-element solution of partial differential equations, especially in the field of semiconductor process and device simulation, the major application is to provide appropriate resolution of the partial discretization mesh. The start-up conditions for semiconductor process and device simulations claim an initial mesh preparation that is performed by so-called Laplace refinement. The basic idea is to solve Laplace's equation on an initial coarse mesh with Dirichlet boundary conditions. Afterward, the gradient field is used to form an anisotropic metric that allows to refine the initial mesh based on tetrahedral bisection

The quality of the numeric approximation of the partial differential equations governing carrier transport in semiconductor devices depends particularly on the grid. The method of choice is to use structurally aligned grids since the regions and directions therein that determine device behavior are usually straightforward to find as they depend on the distribution of doping. Here, the authors present an algorithm for generating structurally aligned grids including anisotropy with resolutions varying over several orders of magnitude. The algorithm is based on a level set approach and permits to define the refined resolutions in a flexible manner as a function of doping. Furthermore, criteria on grid quality can be enforced. In order to show the practicability of this method, the authors study the examples of a trench gate metal-oxide-semiconductor field-effect transistor (TMOSFET) and a radio frequency silicon-on-insulator lateral double diffused metal-oxide-semiconductor (RF SOI LDMOS) power device using the device simulator MINIMOS NT, where simulations are performed on a grid generated by the new algorithm. In order to resolve the interesting regions of the TMOSFET and the RF SOI LDMOS power device accurately, several regions of refinement were defined where the grid was grown with varying resolutions.

We evaluate optimization techniques to reduce the necessary user interaction for inverse modeling applications as they are used in the technology computer-aided design field. Four optimization strategies are compared. Two well-known global optimization methods, simulated annealing and genetic optimization, a local gradient-based optimization strategy, and a combination of a local and a global method. We rate the applicability of each method in terms of the minimal achievable target value for a given number of simulation runs and in terms of the fastest convergence. A brief overview over the three used optimization algorithms is given. The optimization framework that is used to distribute the workload over a cluster of workstations is described. The actual comparison is achieved by means of an inverse modeling application that is performed for various settings of the optimization algorithms. All presented optimization algorithms are capable of evaluating several targets in parallel. The best optimization strategy that is found is used in the calibration of a model for silicon self-interstitial cluster formation and dissolution.

Since Stratton published his famous paper four decades ago, various transport models have been proposed which account for the average carrier energy or temperature in one way or another. The need for such transport models arose because the traditionally used drift-diffusion model cannot capture nonlocal effects which gained increasing importance in modern miniaturized semiconductor devices. In the derivation of these models from Boltzmann's transport equation, several assumptions have to be made in order to obtain a tractable equation set. Although these assumptions may differ significantly, the resulting final models show various similarities, which has frequently led to confusion. We give a detailed review on this subject, highlighting the differences and similarities between the models, and we shed some light on the critical issues associated with higher order transport models.

We deal with problems arising in the coupling of process and device simulators. It is analyzed what kind of data and algorithms such simulations are based on. An overview of existing technology computer-aided design data models is given. A generic object-oriented data model suitable for three-dimensional process and device simulations, the so-called WAFER-STATE-SERVER is presented. By taking advantage of object-oriented abstraction mechanisms, key tasks in the coupling of simulators are relocated from the simulator into the WAFER-STATE-SERVER. The new data model allows an efficient data exchange between existing process and device simulators. It is capable of managing geometries of different dimensions, and handling grids and distributed quantities stored therein. The data model also defines algorithms to perform geometrical operations as they occur in topography simulations. Three process simulators based on the new data model were developed, one of which is presented in this work.

An algorithm for smoothing results of three-dimensional (3-D) Monte Carlo ion implantation simulations and translating them from the grid used for the Monte Carlo simulation to an arbitrary unstructured 3-D grid is presented. This algorithm is important for joining various process simulation steps, where data have to be smoothed or transferred from one grid to another. Furthermore, it is important for integrating the ion implantation simulator into a process flow. One reason for using different grids is that for certain Monte Carlo simulation methods, using orthogrids is mandatory because of performance reasons. The algorithm presented sweeps a small rectangular grid over the points of the new tetrahedral grid and uses approximation by generalized Bernstein polynomials. This approach was put on a mathematically sound basis by proving several properties of these polynomials. It does not suffer from the adverse effects of least squares fits of polynomials of fixed degree as known from the response surface method. The most important properties of Bernstein polynomials generalized to cuboid domains are presented, including uniform convergence, an asymptotic formula, and the variation diminishing property. The smoothing algorithm which works very fast is described and, in order to show its applicability, the resulting values of a 3-D real world implantation example are given and compared with those of a least squares fit of a multivariate polynomial of degree two, which yielded unusable results.

Filling high aspect ratio trenches is an essential manufacturing step for state of the art memory cells. Understanding and simulating the transport and surface processes enables one to achieve voidless filling of deep trenches, to predict the resulting profiles, and thus to optimize the process parameters and the resulting memory cells. Experiments on arsenic doped polysilicon deposition show that under certain process conditions step coverages greater than unity can be achieved. We developed a new model for the simulation of arsenic doped polysilicon deposition, which takes into account surface coverage dependent sticking coefficients and surface coverage dependent arsenic incorporation and desorption rates. The additional introduction of Langmuir-Hinshelwood type time dependent surface coverage enabled the reproduction of the bottom up filling of the trenches in simulations. Additionally, the rigorous treatment of the time dependent surface coverage allows to trace the in situ doping of the deposited film. The model presented was implemented and simulations were carried out for different process parameters. Very good agreement with experimental data was achieved with theoretically deduced parameters. Simulation results are shown and discussed for polysilicon deposition into 0.1 /spl mu/m wide and 7 /spl mu/m deep, high aspect ratio trenches.

We present a parallelization method based on message passing interface (MPI) for a Monte Carlo program for two-dimensional (2-D) and three-dimensional (3-D) simulation of ion implantations. We use a master-slave strategy where the master process synchronizes the slaves and performs the input-output operations, while the slaves perform the physical simulation. For this method the simulation domain is geometrically distributed among several CPU's which have to exchange only very little information during the simulation. Thereby, the communication overhead between the CPU's is kept so low that it has almost no influence on the performance gain even if a standard network of workstations is used instead of a massively parallel computer to perform the simulation. We have optimized the performance gain by identifying bottlenecks of this strategy when it is applied to arbitrary geometries consisting of various materials. This requires the application of different physical models within the simulation domain and makes it impossible to determine a reasonable domain distribution before starting the simulation. Due to a feedback between master and slaves by online performance measurements, we obtain an almost linear performance gain on a cluster of workstations with just slightly varying processor loads. Besides the increase in performance, the parallelization method also achieves a distribution of the required memory. This allows 3-D simulations on a cluster of workstations, where each single machines would not have enough memory to perform the simulation on its own.

The maximum principle is the most important property of solutions to diffusion equations. Violation of the maximum principle by the applied discretization scheme is the cause for severe numerical instabilities: the emergence of negative concentrations and, in the nonlinear case, the deterioration of the convergence of the Newton iteration. We compare finite volumes (FV) and finite elements (FE) in three dimensions with respect to the constraints they impose on the mesh to achieve a discrete maximum principle. Distinctive mesh examples and simulations are presented to clarify the mutual relationship of the resulting constraints: Delaunay meshes guarantee a maximum principle for FV, while the recently introduced dihedral angle criterion is the natural constraint for FE. By constructing a mesh which fulfills the dihedral angle criterion but is not Delaunay we illustrate the different scope of both criteria. Due to the lack of meshing strategies tuned for the dihedral angle criterion we argue for the use of FV schemes in three-dimensional diffusion modeling.

For wafer sizes in state of-the-art semiconductor manufacturing ranging up to 300 mm, the uniformity of processes across the wafer becomes a very important issue. We present a fully three-dimensional model for the feature scale simulation of continuum transport and reaction determined high-pressure chemical vapor deposition processes suitable for the investigation of such nonuniformities. The newly developed three-dimensional approach combines topography simulation, meshing, and finite element method tools, and allows simulations over arbitrary geometries such as structures resulting from nonuniform underlying physical vapor deposition films. This enables the examination of film profile variations across the wafer for multistep processes consisting of low- and high-pressure parts such as Ti/TiN/W plug-fills, Additionally, the model allows a very flexible formulation of the involved gas chemistry and surface reactions and can easily be extended to process chemistries including gas phase reactions of precursors as observed in deposition of silicon dioxide from tetraethylorthosilicate (TEOS). We show simulation examples for a tungsten deposition process, which is applied as last step in a Ti/TiN/W plug-fill. For filling of an L-shaped trench, we show the transition from transport to reaction limited process conditions.

We present a new analytical model to predict the spatial location of amorphous phases in ion-implanted single-crystalline silicon using results of multidimensional Monte Carlo simulations. Our approach is based on the concept of the critical damage energy density. Additionally, the self-annealing of radiation damage during ion implantation is taken into account because this effect is crucial for a correct prediction of amorphization. Two aspects of self-annealing are considered, namely, the temperature and the spatial dependence. The latter is related to the local damage energy density, which is simulated by one-, two-, and three-dimensional modules of our Monte Carlo program MCIMPL of the technology CAD framework VISTA. Therefore, the formation and the shape of amorphous regions in single-crystalline silicon can be predicted as a result of Monte Carlo simulations of ion implantation. The suggested model accurately reproduces the results of direct microscopic observations (XTEM measurements) of amorphous layers in silicon after a silicon self-implantation, which are available for a temperature range of 82-296 K.

A new method for adaptive tessellation of three-dimensional (3-D) grids is presented. A mixed-element decomposition method is introduced for local refinement of fully unstructured grids, consisting of tetrahedra and octahedra. The method preserves the shape of the elements of the initial grid and therefore the element quality. Furthermore, local anisotropies of the initial grid are preserved. The developed implementation allows efficient adaptation and is used in a finite element program for simulation of thermal diffusion processes.

Integrated circuits have evolved to a stage where interconnections significantly limit their performance and functional complexity. We introduce a set of tools to perform highly accurate three-dimensional capacitance and resistance/thermal calculations of interconnect structures. We automatically generate these structures from layout information and a given process description. The main enhancement of our work is that we extract the interconnect characteristics after a complete and accurate topography simulation with previous optional lithography analysis, instead of elementary geometric blocks derived from simple analytical models. The capacitance and resistance/thermal extractor simulators are based on optimized finite-element methods, and the topography simulators use a cellular data-based approach.

Advanced analysis features implemented in the Vienna Integrated System for TCAD Applications simulation environment are presented. These functionalities support automatic experiment generation (design of experiments), model fitting (response surface methodology), optimization, and calibration. They interact with the core modules of the framework supporting the simulation of the manufacturing process and electrical characterization of semiconductor devices. Two examples demonstrate the efficiency of these framework capabilities. The first one shows the optimization of the electrical characteristics of vertical double-diffused metal-oxide-semiconductor (MOS) field-effect transistors. The second example deals with the optimization of analytical doping profiles of MOS transistors.

A rigorous three-dimensional (3-D) simulation method for photoresist exposure and development is presented in which light scattering due to a nonplanar topography is calculated using the Maxwell equations. The method relies on a Fourier expansion of the electromagnetic field and extends the two-dimensional (2-D) differential method to the third dimension. The model accounts for partial coherent illumination and considers the nonlinear bleaching reaction of the photoresist. For the development process, the cellular-based topography simulator has been extended. A detailed description of the theory behind the simulation method is presented, the computational efficiency is discussed, and simulation results are given.

SIMON is a single electron tunnel device and circuit simulator that is based on a Monte Carlo method. It allows transient and stationary simulation of arbitrary circuits consisting of tunnel junctions, capacitors, and voltage sources of three kinds: constant, piecewise linearly time dependent, and voltage controlled. Cotunneling can be simulated either with a plain Monte Carlo method or with a combination of the Monte Carlo and master equation approach. A graphic user interface allows the quick and easy design of circuits with single-electron tunnel devices. Furthermore, as an example of the usage of SIMON, we discuss the essential problem of random background charge and present possible solutions.

Succeeding an earlier paper on the data level, the Viennese Integrated System for Technology CAD Applications (VISTA), an integration and development system for Technology CAD, is presented. Starting with a short overview of TCAD methodology and existing integrated systems, portability and comprehensibility are postulated as key considerations and an application-framework architecture is proposed. The design of VISTA's user interface and task level, presented next, adheres strictly to these guidelines. To enable the cooperation of independent simulation tools, an automatic triangulation-based service is provided by VISTA to resolve inconsistencies in wafer representations. A final example shows how three different simulators, integrated by the framework are used to simulate a planarized, trench-isolated 0.25 /spl mu/m CMOS process.>

A general simulation method for three-dimensional surface advancement has been developed and coupled with physical models for etching and deposition. The surface advancement algorithm is based on morphological operations derived from image processing which are performed on a cellular material representation. This method allows arbitrary changes of the actual geometry according to a precalculated etch or deposition rate distribution and can support very complex structures with tunnels or regions of material which are completely disconnected from other regions. Surface loops which result from a growing or etching surface intersecting with itself are inherently avoided. The etch or deposition rate distribution along the exposed surface is obtained from macroscopic point advancement models which consider information about flux distributions and surface reactions of directly and indirectly incident particles.>

In order to meet the requirements of advanced process and device design, a new generation of technology CAD (TCAD) simulation frameworks is emerging. These are based on a data level providing a common data interchange format. Such a format must be suitable for building simulation databases, and needs to be supported by tools and a procedural interface with multi-language bindings for data storage and retrieval by application programs. In this work, the data level of the Viennese integrated system for TCAD applications (VISTA), which includes the profile interchange format (PIF), the PIF binary file manager (PBFM) and the PIF application interface (PAI), is described from a framework point of view.>

A hybrid simulator suitable for modeling small semiconductor devices has been developed in which Monte Carlo and drift-diffusion models are combined. In critical device regions, the position-dependent coefficients of an extended drift-diffusion equation are extracted from a Monte Carlo simulation. Criteria for identifying these regions are described. Additional features which make the code more efficient are presented. First, a free-flight time calculation method using a new self-scattering algorithm is described. It allows for an efficient reduction of self-scattering events. Second, a unique Monte Carlo-Poisson coupling scheme has been developed which converges faster than all presently known schemes. It exploits the so-called Monte Carlo-drift diffusion coupling technique, which also forms the basis of the hybrid method. The simulator has been used to model submicron MOSFET's with gate lengths down to 0.15 /spl mu/m. In addition to the non-local effects occurring in these devices, the performance of the hybrid simulation method is analyzed.>

The authors present an accurate new method for the calculation of the contact currents in a device simulation program which is applicable to arbitrarily shaped device geometries. The method is based on the evaluation of a volume integral of the calculated current densities over the whole device area with a suitably chosen weight function. Different types of weight functions are discussed and compared with the commonly used line integral along the contact. The results are illustrated by three examples: an I/sup 2/L memory cell, an MOS transistor, and a resistor with a reverse-biased diode.>

Article Three-dimensional simulation of semiconductor devices on supercomputers Share on Authors: K. P. Traar SIEMENS AG Austria, Electronic Development, Gudrunstrasse 11, A-1101 Wien, Austria SIEMENS AG Austria, Electronic Development, Gudrunstrasse 11, A-1101 Wien, AustriaView Profile , M. Stiftinger Technical University Vienna, Institute for Microelectronics, Gusshausstrasse 27-29, A-1040 Wien, Austria Technical University Vienna, Institute for Microelectronics, Gusshausstrasse 27-29, A-1040 Wien, AustriaView Profile , O. Heinreichsberger Technical University Vienna, Institute for Microelectronics, Gusshausstrasse 27-29, A-1040 Wien, Austria Technical University Vienna, Institute for Microelectronics, Gusshausstrasse 27-29, A-1040 Wien, AustriaView Profile , S. Selberherr Technical University Vienna, Institute for Microelectronics, Gusshausstrasse 27-29, A-1040 Wien, Austria Technical University Vienna, Institute for Microelectronics, Gusshausstrasse 27-29, A-1040 Wien, AustriaView Profile Authors Info & Claims ICS '91: Proceedings of the 5th international conference on SupercomputingJune 1991 Pages 154–162https://doi.org/10.1145/109025.109069Online:01 June 1991Publication History 0citation483DownloadsMetricsTotal Citations0Total Downloads483Last 12 Months2Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

An attempt was made to optimize the performance of 3D-MINIMOS on a SIEMENS/Fujitsu VP 200. Jacobi and incomplete LU-factorization methods were investigated along with various hand tuning options. Results are compared with those obtained on a Cray-2 and an ALLIANT/FX40 minisupercomputer.>

A simulation method that takes into account effects at the channel edge due to nonplanar interfaces is introduced. The authors applied the box integration method after Forsythe (1960) for discretization. The most important nonplanar interface occurs at the transition of the gate oxide to the field oxide, which is commonly called bird's beak. Approximating this interface with right angles leads to unrealistic results. The authors introduce the numerical treatment in three-dimensional MOSFET simulation with nonplanar interfaces. The physical model used is presented, and the numerical implementation of the basic equations is shown. The simulations have been carried out with MINIMOS 5 a fully three-dimensional simulation program. Three-dimensional effects such as threshold shift for small-channel devices, channel narrowing, and the enhanced conductivity at the channel edge have been successfully modeled.>

The MINIMOS simulation program has been extended to three dimensions to investigate the parasitic effects at the channel edge on MOSFET device characteristics. The box integration method after Forsythe has been applied for discretization. This method is suitable for nonplanar interfaces. The most important nonplanar interface occurs at the transition of the gate oxide to the field oxide called the bird's beak. Approximating this interface as a rectangular shape leads to unrealistic results. The oxide-body is defined by analytical functions, so it is easy to investigate a wide range of applications. An automatic grid-refinement algorithm is used to generate the specific grid. The simulation shows that the influence of the channel edge is not negligible for channel widths less than 2 mu m. The total drain current for narrow channel MOSFETs is either increased or decreased by parasitic three-dimensional effects compared to wide channel (two-dimensional) MOSFETs depending on the bias conditions.>

Until now, rigorous Monte Carlo simulations of ion implantation into 3-D structures have been prohibited by the large amount of computer time required, and 2-D simulations have been restricted to simple structures like linear mask edges or rectangular trenches. Methods are presented which made 2-D simulations with arbitrary geometries as well as 3-D simulations with simple geometries feasible. First, an auxiliary grid is used to reduce the time required to check whether an ion crosses a boundary. Second, each ion trajectory is used several times to determine the history of ions entering the target at different positions. The methods are demonstrated by three examples: implantation into a rectangular trench, implantation into a 2-D trench with nonplanar sidewalls, and implantation into a 3-D trench with quadratic cross section.>

An analytical model for the description of ion-implantation-induced damage profiles is presented. The model is based on extensive Monte Carlo simulations of B-, P-, As-, and Sb-implantations in Si. One-dimensional profiles are described by a Gaussian function and an exponential function joined together continuously with continuous first derivatives. The two-dimensional model has previously been developed by the authors for dopant profiles and is demonstrated to apply well to point defect distributions. Parameters have been obtained for the four ions by fitting the model to the Monte Carlo results, and they are provided in the form of tables for the energy range of 10-300 keV (for the 1D model 1-300 keV). The Monte Carlo simulations are based on the binary collision approximation, the assumption of a random target, and the validity of the linear collision cascade theory. The importance of energy transport by recoils is pointed out.>

Due to the advances in device miniaturization it is often necessary to get a better understanding of the physical fabrication processes by applying advanced physical models. Since existing process modeling programs can handle only specific physical quantities, we have developed general purpose solvers for one and two space dimensions which are able to treat an arbitrary number of coupled partial differential equations for physical quantities. In the paper we will show the general formulation of the equations which can be solved. We deal with the user-interface of the programs and the numerical problems one has to face. To demonstrate the capabilities of the programs we will show typical applications.

This paper gives guidelines for the development of computer programs for the numerical simulation of semiconductor devices. For this purpose, the basic mathematical results on the corresponding elliptic boundary value problem are reviewed. Particularly, existence, smoothness, and structure of the solutions of the fundamental semiconductor equations are discussed. Various feasible approaches to the numerical solution of the semiconductor equations are described. Much emphasis is placed on constructive remarks to help authors of device simulation programs make decisions on their code design problems. Thus criteria for an optimal mesh generation strategy are given. The iterative solution of the systems of nonlinear and linear equations obtained by discretizing the semiconductor equations is discussed. An example shows the power of these concepts combined with modern numerical methods in comparison to classical approaches.

An accurate two-dimensional self-consistent numerical model for MOS transistors which is able to predict avalanche behavior is presented. This model aims at a more principal understanding of the physical processes which arise from the avalanche effect and which eventually lead to breakdown. The system of the fundamental semiconductor equations with several generation/recombination mechanisms is solved. To improve the description of the ionization process, correction terms are introduced which account for the fact that the gate induced field does not cause ionization. Holes which are generated in the pinch-off region by impact ionization cause a bulk current; the voltage drop at the parasitic bulk resistance initiates an internal feedback mechanism. Thus a negative resistance branch of the drain current characteristic can arise. However, at high current levels, introduced by a high gate bias and/or a short channel, this snap-back effect is often counterbalanced by strong recombination. Snapback voltage can be estimated with this model.