This benchmark presentation made by Arm Ltd and its subsidiaries (Arm) contains forward-looking statements and information. The information contained herein is therefore provided by Arm on an “as-is“ basis without warranty or liability of any kind. While Arm has made every attempt to ensure that the information contained in the benchmark presentation is accurate and reliable at the time of its publication, it cannot accept responsibility for any errors, omissions or inaccuracies or for the results obtained from the use of such information and should be used for guidance purposes only and is not intended to replace discussions with a duly appointed representative of Arm. Any results or comparisons shown are for general information purposes only and any particular data or analysis should not be interpreted as demonstrating a cause and effect relationship. Comparable performance on any performance indicator does not guarantee comparable performance on any other performance indicator.

This article consists of a collection of slides from the author's conference presentation.

A modern digital system includes in a single chip many components: processing cores, large caches, memory controllers, and hardware accelerators. Looking forward, future semiconductor technologies will enable even higher device integration, overall increasing system performance while reducing energy consumption. Unfortunately, prominent experts agree that such technologies will be prone to both permanent and transient faults within their lifetime. With the goal of addressing this issue, we propose Cardio: a low-cost architecture for reliable chip multiprocessors. Our solution is based on a novel hardware/software co-design where silicon failures are detected in hardware and system reconfiguration is managed in software. Comparing Cardio with a state-of-the-art hardware-based resiliency solution, Immunet, we found that our design can achieve a comparable fault response time while requiring a much lower area overhead. The proposed solution relies on a distributed resource manager to collect information about a CMP component's health, and leverages a synchronized distributed control mechanism to recover from permanent failures. Such architecture can operate as long as at least one general-purpose processor is still functional. Our experimental evaluation indicates that the overall performance impact of Cardio is as low as 4.5%, and its dynamic reconfiguration time upon fault detection is comprised between 20 and 50 thousand cycles.

The capabilities of mobile devices have been increasing at a momentous rate. As better processors have merged with capable cameras in mobile systems, the number of computer vision applications has grown rapidly. However, the computational and energy constraints of mobile devices have forced computer vision application developers to sacrifice accuracy for the sake of meeting timing demands. To increase the computational performance of mobile systems we present EVA. EVA is an application-specific heterogeneous multicore having a mix of computationally powerful cores with energy efficient cores. Each core of EVA has computation and memory architectural enhancements tailored to the application traits of vision codes. Using a computer vision benchmarking suite, we evaluate the efficiency and performance of a wide range of EVA designs. We show that EVA can provide speedups of over 9× that of an embedded processor while reducing energy demands by as much as 3×.

The HAMSTRAD microwave instrument operates at 60 and 183 GHz and measures temperature and water vapor, respectively, from 0- to 10-km altitude with a time resolution of 7 min. The radiometer has been successfully deployed at Dome C (Concordia Station), Antarctica (75°06' S, 123°21' E, 3233 m amsl) during the first summertime campaign for 12 days in January-February 2009. The radiometer has been continuously running since January 2010, hosted within a dedicated shelter. We have used the very first set of HAMSTRAD data, recorded when the instrument was outdoors, to assess its potential to sound the troposphere over Dome C, from the planetary boundary layer (PBL) up to the tropopause ( ~ 6 km above surface, ~ 9 km amsl). We have compared the HAMSTRAD measurements to several sets of measurements performed at the Dome-C station or in its vicinity: meteorological radiosondes, in situ PT100 and Humicap sondes along the vertical extent of a 45-m tower, meteorological sensor attached to the HAMSTRAD instrument, and the spaceborne Infrared Atmospheric Sounding Interferometer (IASI) instrument onboard the EUMETSAT MetOp-A satellite in polar orbit. The variability of integrated water vapor (IWV) observed by HAMSTRAD with extremely low values of 0.5 kg ·m-2was also measured by the radiosondes (very high HAMSTRAD versus radiosonde correlation of 0.98), whereas IASI cloud-free measurements did not reproduce well the HAMSTRAD IWV variation (weak HAMSTRAD versus IASI correlation of 0.58). The measurements of absolute humidity (H2O) from HAMSTRAD at Dome C cover a large vertical extent from the surface to about 6 km above surface with a high sensitivity in the free troposphere. The strong diurnal variation of H2O observed by the in situ sensors in the PBL is not well detected by the radiometer. In the free troposphere, the HAMSTRAD versus radiosonde H2O correlation can reach 0.8-0.9. Around the tropopause, HAMSTRAD shows the same variability as IASI and radiosondes but with a dry bias of 0.01 g ·m-3. HAMSTRAD tends to show a wetter atmosphere by 0.1-0.3 g ·m-3compared with radiosondes from the surface to ~ 2-km altitude and a drier atmosphere above by ~ 0.1g ·m-3. The sensitivity of the temperature profiles from HAMSTRAD is very high in the PBL and in the free troposphere but degrades around the tropopause. The strong diurnal signal measured above the surface by HAMSTRAD (3-6 K) is consistent with all the other in situ data sets. The temporal evolution over the 12-day period in the PBL is also consistent with all other data sets (radiosondes, IASI, in situ sondes, and meteorological sensors). In the free troposphere and around the tropopause, the HAMSTRAD temporal evolution is consistent with that observed by radiosondes and IASI, although a cold bias exists compared with IASI and radiosondes around the tropopause. For heights less than 4 km above surface, HAMSTRAD correlates very well with radiosondes and in situ sensors (correlation better than 0.8) but less well with IASI (0.4). Below the tropopause, the IASI and HAMSTRAD correlation reaches 0.9, whereas above the tropopause, the correlation of IASI and radiosondes with HAMSTRAD is rather low (2O and temperature have little sensitivity. Based upon 5-day back trajectory analyses, the great variability of H2O and temperature above Dome C as measured by the different instruments from the surface up to the tropopause over the 12-day period can be explained by the origin of air masses. The Dome-C site is found to be under the influence of the oceanic middle latitudes and the Antarctic coastal latitudes, but on some occasions, the air masses originated from the Antarctic continent are associated with colder and drier episodes.

Current technology scaling is leading to increasingly fragile components, making hardware reliability a primary design consideration. Recently researchers have proposed low-cost reliability solutions that detect hardware faults through software-level symptom monitoring. SWAT (SoftWare Anomaly Treatment), one such solution, demonstrated with microarchitecture-level simulations that symptom-based solutions can provide high fault coverage and a low Silent Data Corruption (SDC) rate. However, more accurate evaluations are needed to validate such solutions for hardware faults in real-world processor designs. In this paper, we evaluate SWAT's symptom-based detectors on gate-level faults using an FPGA-based, full-system prototype. With this platform, we performed a gate-level accurate fault injection campaign of 51,630 fault injections in the OpenSPARC T1 core logic across five SPECInt 2000 benchmarks. With an overall SDC rate of 0.79%, our results are comparable to previous microarchitecture-level evaluations of SWAT, demonstrating the effectiveness of symptom-based software detectors for permanent faults in real-world designs.

The reliability of future processors is threatened by decreasing transistor robustness. Current architectures focus on delivering high performance at low cost; lifetime device reliability is a secondary concern. As the rate of permanent hardware faults increases, robustness will become a first class constraint for even low-cost systems. Current research into reliable architectures has focused on ad-hoc solutions to improve designs without altering their centralized control logic. Unfortunately, this centralized control presents a single point of failure, which limits long-term robustness.To address this issue, we introduce Viper, an architecture built from a redundant collection offine-grained hardware components. Instructions are perceived as customers that require a sequence of services in order to properly execute. The hardware components vie to perform what services they can, dynamically forming virtual pipelines that avoid defective hardware. This is done using distributed control logic, which avoids a single point offailure by construction. Viper can tolerate a high number of permanent faults due to its inherent redundancy. As fault counts increase, its performance degrades more gracefully than traditional centralized-logic architectures. We estimate that fault rates higher than one permanentfaults per 12 million transistors, on average, cause the throughput of a classic CMP design to fall below that of a Viper design of similar size.

For any computing system to be secure, both hardware and software have to be trusted. If the hardware layer in a secure system is compromised, not only it would be possible to extract secret information about the software, but it would also be extremely hard for the software to detect that an attack is underway. In this work we detail a complete end-to-end fault-attack on a microprocessor system and practically demonstrate how hardware vulnerabilities can be exploited to target secure systems. We developed a theoretical attack to the RSA signature algorithm, and we realized it in practice against an FPGA implementation of the system under attack. To perpetrate the attack, we inject transient faults in the target machine by regulating the voltage supply of the system. Thus, our attack does not require access to the victim system's internal components, but simply proximity to it. The paper makes three important contributions: first, we develop a systematic fault-based attack on the modular exponentiation algorithm for RSA. Second, we expose and exploit a severe flaw on the implementation of the RSA signature algorithm on OpenSSL, a widely used package for SSL encryption and authentication. Third, we report on the first physical demonstration of a fault-based security attack of a complete microprocessor system running unmodified production software: we attack the original OpenSSL authentication library running on a SPARC Linux system implemented on FPGA, and extract the system's 1024-bit RSA private key in approximately 100 hours.

Extreme technology scaling in silicon devices drastically affects reliability, particularly because of runtime failures induced by transistor wearout. Current online testing mechanisms focus on testing all components in a microprocessor, including hardware that has not been exercised, and thus have high performance penalties. We propose a hybrid hardware/software online testing solution where components that are heavily utilized by the software application are tested more thoroughly and frequently. Thus, our online testing approach focuses on the processor units that affect application correctness the most, and it achieves high coverage while incurring minimal performance overhead. We also introduce a new metric, Application-Aware Fault Coverage, measuring a test's capability to detect faults that might have corrupted the state or the output of an application. Test coverage is further improved through the insertion of observation points that augment the coverage of the testing system. By evaluating our technique on a Sun OpenSPARC T1, we show that our solution maintains high Application-Aware Fault Coverage while reducing the performance overhead of online testing by more than a factor of 2 when compared to solutions oblivious to application's behavior. Specifically, we found that our solution can achieve 95% fault coverage while maintaining a minimal performance overhead (1.3%) and area impact (0.4%).

Extreme scaling practices in silicon technology are quickly leading to integrated circuit components with limited reliability, where phenomena such as early-transistor failures, gate-oxide wearout, and transient faults are becoming increasingly common. In order to overcome these issues and develop robust design techniques for large-market silicon ICs, it is necessary to rely on accurate failure analysis frameworks which enable design houses to faithfully evaluate both the impact of a wide range of potential failures and the ability of candidate reliable mechanisms to overcome them. Unfortunately, while failure rates are already growing beyond economically viable limits, no fault analysis framework is yet available that is both accurate and can operate on a complex integrated system. To address this void, we present CrashTest, a fast, high-fidelity and flexible resiliency analysis system. Given a hardware description model of the design under analysis, CrashTest is capable of orchestrating and performing a comprehensive design resiliency analysis by examining how the design reacts to faults while running software applications. Upon completion, CrashTest provides a high-fidelity analysis report obtained by performing a fault injection campaign at the gate-level netlist of the design. The fault injection and analysis process is significantly accelerated by the use of an FPGA hardware emulation platform. We conducted experimental evaluations on a range of systems, including a complex LEON-based system-on-chip, and evaluated the impact of gate-level injected faults at the system level. We found that CrashTest is 16-90x faster than an equivalent software-based framework, when analyzing designs through direct primary I/Os. As shown by our LEON-based SoC experiments, CrashTest exhibits emulation speeds that are six orders of magnitude faster than simulation.