Area efficient self-correcting flip-flops for use with triple modular redundant (TMR) soft-error hardened logic are implemented in a 12-nm finFET process technology. The TMR flip-flop slave latches self-correct in the clock low phase using Muller C-elements in the latch feedback. These C-elements are driven by the two redundant stored values and not by the slave latch itself, saving area over a similar implementation using majority gate feedback. These flip-flops are implemented as large shift-register arrays on a test chip and have been experimentally tested for their soft-error mitigation in static and dynamic modes of operation using heavy ions and protons. We show how high clock skew can result in susceptibility to soft-errors in the dynamic mode, and explain the potential failure mechanism.

This work discusses the ASAP7 predictive process design kit (PDK) and associated standard cell library. The necessity for multi-patterning (MP) techniques at advanced nodes results in the standard cell and SRAM architecture becoming entangled with design rules, mandating design-technology co-optimization (DTCO). This paper discusses the DTCO process involving standard cell physical design. An assumption of extreme ultraviolet (EUV) lithography availability in the PDK allows bi-directional M1 geometries that are difficult with MP. Routing and power distribution schemes for self-aligned quadruple patterning (SAQP) friendly, high density standard cell based blocks are shown. Restrictive design rules are required and supported by the automated place and route (APR) setup. Supporting sub-20 nm dimensions with academic tool licenses is described. The APR (QRC techfile) extraction shows high correlation with the Calibre extraction deck. Finally, use of the PDK for academic coursework and research is discussed.

SRAMs are ubiquitous in modern VLSI design but have become difficult to design in advanced finFET processes due to fin quantization and large variability at small geometries. In this paper six transistor SRAM design on a 7-nm predictive PDK is presented. The SRAMs use differential sense amplifier based sensing to support long bit-lines and high array efficiency. Different SRAM cells are evaluated statistically, resulting in the choice of a 122 cell due to its easier lithography and superior write margins. A novel switched capacitor reduced column VDD is presented, which has excellent across corner voltage characteristics and speed. The analysis shows yield to a minimum VDD of 500 mV.

A radiation hardened by design embedded microprocessor is presented. The design uses multiple approaches to minimize the performance reduction from hardening, while simultaneously limiting the power increase. The speculative portions of the pipeline are protected by microarchitecture approaches, i.e., the speculative pipeline is dual redundant, whereby instructions that have errors in one copy cause a pipeline restart - only matching results commit to architectural state. The register file is dual redundant with mechanisms for correction using one copy whose parity is correct. The data cache memory is write-through, allowing protection with parity. The remaining architectural state is protected via hardened circuits. These are implemented with self-correcting triple mode redundant (TMR) flip-flops and TMR logic. The design, implemented here on a 90-nm bulk CMOS process, achieves unprecedented single event effects hardness and 400+ MHz operating frequency at less than 500 mW power consumption. The main constituent circuit hardening approaches have been fabricated and tested separately. Broad beam testing of the constituent circuits has resulted in no uncorrectable soft errors below 100 MeV-cm2/mg LETEFF. We describe the CAD flows used to ensure node separation to achieve high immunity to multiple node charge collection and discuss the relative costs of the chosen hardening techniques.

Integrated circuit (IC) identification using unclonable digital fingerprints facilitates the authentication of ICs, device tracking, and cryptographic functions. In this paper, we present two hardware methods exploiting the inherent process-induced mismatch of SRAM cells. The proposed circuits improve upon those previously published by reducing the number of bits that vary from trial to trial, and can be used at times other than just IC power-up. The proposed circuits and methods are compared with the previous power-up approach using the experimental results from a 90-nm test chip. The required SRAM array periphery circuit changes allow the use of standard foundry SRAM cells and do not impact the memory access time.

Hardening the flip-flops and latches is the most straightforward way to improve the soft-error robustness of sequential logic circuits. This paper presents novel pulse-clocked latch based flip-flops that mitigate not just single event upsets (SEUs) but also single event transients (SETs) that are an increasing threat in high performance logic. The design uses triple-mode redundant latches, combined with appropriate clocking to provide redundancy in both space and time. Analysis of the flip-flop operation and immunity to both SEUs and SETs, as well as layout that provides adequate critical node separation to prevent multi-node charge collection failures, are presented. The multi-bit flip-flop macro has been fabricated and tested functional as shift registers on a 90-nm foundry LP process.

A simple macro-model to accurately simulate upset error on CMOS devices is presented. This macro-model can accurately simulate the typical behavior of single event effect (SEE) caused by ionizing radiation charge collection at N type and P type diffusions. The model is calibrated using 3-D mixed mode technology computer aided design (TCAD) device simulations and implemented as a SPICE circuit macro-model. The model uses a dependent current source with a Weibull distribution to model the current injection on circuit node. The model shows physical response and adjusting parameters allows high accuracy to the 3-D TCAD simulated response.

Register file (RF) memory is important in low power SOCs due to its inherent low voltage stability. Moreover, designs increasingly use compiled instead of custom memory blocks, which frequently employ static, rather than pre-charged dynamic register files. In this paper, we compare static and dynamic RF power dissipation and timing characteristics. The relative timing and power advantages of the designs are shown to be dependent on the memory aspect ratio, i.e. array width and height. One version, fabricated on a foundry bulk CMOS 90-nm low standby power (LP) process provides a baseline for the analyses.

In this paper, we describe a six-transistor static random access memory (SRAM) cell optimization methodology for transistors with significantly improved matching, while maintaining compatibility with the baseline design. We briefly describe the reduced AVTtransistors and show that they allow substantially improved minimum SRAM operating voltage (Vmin) and improved array leakage. Using an efficient design of experiments (DOE) factorial as a pseudo-Monte Carlo generator, points on the tail of the distribution are directly simulated. The highly efficient method is shown to allow optimization and `what if' scenario investigations. Simulation and silicon results on a 65-nm process as well as simulation results on a 28-nm process are shown.

In this paper a single-cycle issue queue circuit architecture that simplifies the wakeup and selection logic is proposed. The micro-architecture and fully static CMOS circuits are presented for a 32-entry queue that issues four instructions per cycle. The instruction-ready signals are divided into groups and processed in parallel to issue the four oldest ready instructions. The complete issue queue and prioritization logic requires 20 inversions, allowing simulated circuit operation at over 4 GHz in a foundry 45 nm SOI fabrication process.

A monolithic switched-capacitor voltage converter to drive the virtual Vss for low standby power "drowsy" modes is presented. The voltage converter has been fabricated on a 0.13-μm digital CMOS process. Test chip measurements demonstrate current drive capability from 10 μA to 100 μA with power efficiency over 86%. The test chip measurements also demonstrate that the chip level power efficiency of the converter is at least 2x better than the conventional linear regulation approach, which is commonly used in high volume commercially available designs.

A ring oscillator based test structure with special power multiplexing to allow accurate active and standby (leakage) power measurements with minimal test chip pin count is presented. This structure is used to validate radiation hardened by design (RHBD) standard cell library gates for TID hardness and delay. Additionally, the performance of standard commercial two-edge gates and their annular counterparts are also compared experimentally. The gate delay and energy per transition is shown to be significantly increased for some RHBD gates over their two-edge counterparts. Large ring oscillator delay variations are also shown, even with all test die from the same wafer.

An internet protocol (IP) router determines the next hop for a packet by finding the longest prefix match. This lookup often occurs in ternary content addressable memory (TCAM), which allows bit masking of the IP address. In this paper, an internet protocol content addressable memory (IPCAM) circuit that directly determines the longest prefix match to the stored address is described. The proposed IPCAM produces an encoded prefix match length that is limited by the prefix mask. Entries need not be sorted in order. One of the proposed IPCAM entries replaces on average 22 TCAM entries. Consequently the longest prefix matching CAM is less than 1/10 the size of the equivalent TCAM and dissipates 93.5% less dynamic power. The encoded outputs drive a priority encoder to determine the longest prefix match in the IPCAM arrays. A priority encoder circuit architecture appropriate to the unsorted IPCAM entries is also presented.

Measurement and extraction of as fabricated SRAM cell variability is essential to process improvement and robust design. This is challenging in practice, due to the complexity in the test procedure and requisite numerical analysis. This work proposes a new singleended test procedure for SRAM cell write margin measurement. Moreover, an efficient decomposition method is developed to extract transistor threshold voltage (VTH) variations from the measurements, allowing accurate determination of SRAM cell stability. The entire approach is demonstrated in a 90nm test chip with 32K cells. The advantages of the proposed method include: (1) a single-ended SRAM test structure with no disturbance to SRAM operations; (2) a convenient test procedure that only requires quasistatic control of external voltages; and (3) a non-iterative method that extracts the VTH variation of each transistor from eight measurements. The new procedure enables accurate predictions of SRAM performance variability. As validated with 90nm data of write margin and data retention voltage, the prediction error from extracted VTH variations is < 4% at all corners.

A fundamental property of superscalar architectures is the execution of multiple instructions per cycle. To accomplish this, the issue logic selects and prioritizes the instructions whose operands will be ready in the next cycle, using wakeup, select and queue update logic. By incorporating the issue logic in one pipeline stage, dependent instructions can be issued in consecutive cycles. However, the many serial operations required makes this problematic from a circuit delay perspective. In this paper, we propose an issue queue design that divides the ready signals into groups, sorts the groups in parallel and provides four oldest ready instructions for issue, with single-cycle operation. Static CMOS select and update logic reduces power and low fan-out in many stages improves circuit speed. The complete issue logic requires 30 inversions, allowing simulated circuit operation at over 3 GHz in a foundry 45nm SOI fabrication process.

Translation lookaside buffers (TLB) are an essential component to speed up virtual to physical address translation in modern microprocessors. Here, hierarchical NAND content addressable memory (CAM) match lines are used to achieve low power. Simulations on a 65 nm foundry process show single-cycle accesses with a clock to physical address output delay of 168 ps. For large (16MB) page sizes the match line energy is reduced up to 81% compared to NOR match lines.

The design of high speed, compact and low power priority encoder circuits using static CMOS gates is presented. The proposed hierarchical static design has improved delay and power compared to a dynamic domino circuit implementation. For an 8-bit priority encoder design the proposed approach shows 77.1% power dissipation, 63.6% transistor count and 36% delay improvement. The improvement increases with the number of priority encoder bits, with a delay improvement of 41.2% for a 16 inputs design.

An IP router determines the next hop for an internet protocol packet by finding the longest prefix match. Ternary CAMs, which allow bit masking of the IP address, are commonly used for this fast search function. In this paper, a CAM that directly determines the longest prefix match to the stored address is described. One of these best matching (IPCAM) entries replaces on average 22 TCAM entries. Overall, the resulting IPCAM array is less than 1/10 the size of the equivalent TCAM and dissipates 93.5% less dynamic power. The design automatically produces an encoded prefix match length that is limited by the prefix mask, so entries do not need to be sorted in prefix mask length order. Simulations of extracted layouts in a bulk CMOS 65-nm foundry process show the proposed IPCAM circuits can operate above 1 GHz

An analytical gate delay model is developed by integrating short-channel effects and the Alpha-power law-based timing model. As verified with an industrial 90-nm technology, this analytical approach accurately predicts both nominal delay and delay variability over a wide range of power supply conditions including subthreshold and strong- inversion regions. Excellent model scalability enables efficient mapping between process variations and delay variability at the gate level. Based on this model, the impact of various physical effects on delay variability has been identified. While the variation of effective channel length is the leading source for delay variability at the current 90-nm node, delay variability is actually more sensitive to the variation of threshold voltage, especially in the subthreshold region. Furthermore, the limitation of low-power design techniques is investigated in the presence of process variations, particularly dual Vthand L biasing. These techniques become less effective at low VDDdue to excessive delay variability.

The design of programmable logic arrays using NAND-NOR gates for the AND and OR logic planes, respectively, instead of the conventional NOR-NOR planes is described. The circuit architecture uses a hierarchical tree of four input domino NAND gates to implement the AND plane. The OR plane is split in two for increased speed and robustness. The circuits as well as timing and power advantages are described. Simulations on a foundry 130 nm process show nearly 50% power savings at less than 10% delay cost, primarily due to lower AND plane activity factor and reduced clock loading.

Content addressable memory (CAM) is used in fully associative VLSI lookup circuits for cache memory, translation lookaside buffers (TLBs), and in Internet Protocol (IP) address comparison. In this paper, the use of dynamic nand match lines is investigated and compared to conventional nor match lines in cache applications. To achieve high speed, a hierarchical match line is used. The dynamic stack charge-sharing noise immunity, speed, and actual power savings over a conventional nor match line are investigated using benchmark data. While random patterns are often used when benchmarking CAM match line power, it is shown to be optimistic compared to address trace data, since addresses are highly correlated. It is also shown that proper address input ordering can provide additional power savings. A simple model for the power in dynamic circuit stacks is derived and compared to power simulation data. Additionally, impact on cache tag area and the scaling of the nand stack to future processes is described

A physical yet compact gate delay model is developed integrating short-channel effects and the Alpha-power law based timing model. This analytical approach accurately predicts both nominal delay and delay variability over a wide range of bias conditions, including sub-threshold. Excellent model scalability enables efficient mapping between process variations and delay variability at the circuit level. Based on this model, relative importance of physical effects on delay variability has been identified. While effective channel length variation is the leading source for variability at current 90nm node, performance variability is actually more sensitive to threshold variation at the sub-threshold region. Furthermore, this model is applied to investigate the limitation of low power design techniques in the presence of process variations, particularly dual Vth and L biasing. Due to excessive variability under low VDD, these techniques become ineffective.

Operating CMOS circuits with power supplies below the threshold voltage has been suggested for ultra-low power systems. High fan-in or fan-out circuits, such as those in memories, are prone to failure when operating in this regime. Vanishing noise margins due to reduced transistor on-to-off current ratios result in circuit failure as the supply voltage shrinks. Therefore, design guidelines for robust subthreshold logic circuit are developed in this paper. First, an analytical model is derived to determine a circuit's fan-in/out limitations and the minimum supply voltage for robust subthreshold operation. Excellent agreement between the analytical model and circuit simulations is shown. This model is applied to the analysis of circuit robustness as affected by design choices, both systematic and random processing variations, supply voltage fluctuations, and temperature variations.

Scaling has allowed rising transistor counts per die and increases leakage at an exponential rate, making power a primary constraint in all integrated circuit designs. Future designs must address emerging leakage components due to direct band to band tunneling, through MOSFET oxides and at steep junction doping gradients. In this paper, we describe circuit design techniques for managing leakage power, both during standby and for limiting the leakage power contribution during active operation. The efficacy, design effort, and process ramifications of different approaches are examined. The schemes are primarily aimed at hand-held devices such as cell phones, since the needs for low power are most acute in these markets due to limited battery capacity.

Integrated circuits fabricated on a low-leakage process typically display lower performance due to the high threshold voltage (V/sub t/) transistors. Higher performance microprocessors sacrifice power efficiency by decreasing V/sub t/. We show that a processor built on a low V/sub t/ process can achieve the power-per-computation characteristics of one built using a high V/sub t/ process, by using a "drowsy" mode combining reverse body bias (RBB) and voltage collapse when idle. This approach also allows for higher peak performance, if needed. A simple power model is shown to accurately match the measured data; high-operational frequency is demonstrated when in active operation. The circuit techniques used to provide the RBB mode of operation are described and compared with other techniques such as multi-threshold CMOS. While both techniques can be effective for logic, the design effort for RBB is shown to be smaller, while reducing embedded static random access memory standby power without added size.

Lowering active power dissipation is increasingly important for battery powered embedded microprocessors. Here, power reduction techniques applicable to fully associative translation lookaside buffers, as well as other associative structures and dynamic register files, are described. Powermill simulations of implementation in a microprocessor on 0.18mm process technology demonstrate 42% power savings. Circuit implementations, as well as architectural simulations demonstrating applicability to typical instruction mixes are shown.

Static power dissipation is a concern for battery powered hand-held devices since it can substantially impact the battery life. Here, the use of reverse body bias to limit Ioff on the high performance, low power XScale™ microprocessor core is described. The scheme utilized is amenable to implementation on a low-cost (non-triple well) process and has limited regulation requirements. The regulation requirements and circuits are described, as is the performance of the method. A measured current reduction factor of over 25 is achieved with this method of reverse body bias. Implications of the use of body bias leakage control for active power and performance, as well as system level implications are also discussed.

The embedding of neural networks in real-time systems performing classification and clustering tasks requires that models be implemented in hardware. A flexible, pipelined associative memory capable of operating in real-time is proposed as a hardware substrate for the emulation of neural fixed-radius clustering and binary classification schemes. This paper points out several important considerations in the development of hardware implementations. As a specific example, it is shown how the ART1 paradigm can be functionally emulated by the limited resolution pipelined architecture, in the absence of full parallelism.