This paper describes the functional verification effort during a specific hardware development program that included three of the largest ASICs designed at Nortel. These devices marked a transition point in methodology as verification took front and centre on the critical path of the ASIC schedule. Both the simulation and emulation strategies are presented. The simulation methodology introduced new techniques such as ASIC sub-system level behavioural modeling, large multi-chip simulations, and random pattern simulations. The emulation strategy was based on a plan that consisted of integrating parts of the real software on the emulated system. This paper describes how these technologies were deployed, analyzes the bugs that were found and highlights the bottlenecks in functional verification as systems become more complex.

This paper describes a functional hardware verification methodology for ASIC intensive products. It spans the ASIC, board, and system level, enabling simulation of the design concurrent with ASIC and board development. The simulation strategy relies on rapid development of behavioural models of ASICs to enable work to proceed in parallel and to achieve the necessary simulation efficiency. The results from a project on which the methodology was used are presented. The process provided early visibility of over 200 issues in the system of which 32 were critical to the successful conformance and timely completion of the project.

A subthreshold model for use in circuit simulation software is described. The model includes representation of nonuniform substrate impurity concentrations and short-channel and narrow-channel effects, while being simple in form. It has been developed in concert with an automated parameter-extraction methodology. The model adds only one parameter to the existing strong inversion model with which it is fully integrated. The accuracy and computational efficiency are suitable for circuit simulation. The results of an extraction carried out on nMOS transistors with channel widths from 70 to 0.9 mu m and channel lengths from 35 to 1.25 mu m over a wide range of bias conditions are described.>