A multimode source/channel coder which can dynamically control the balance of source and channel coding according to the channel quality is introduced. As an example of such a system, a 4.8-kb/s code excited linear predictive coder with three coding modes (A, B1, and B2), each of which has different bit assignments to source and channel coding, is presented. The optimum coding mode is selected in each frame, based on an evaluation of the spectral distortion (SN/sub LAR/) in reproduced speech. The threshold value of SN/sub LAR/ for mode decision is varied according to the channel error rate. Computer simulation shows that 2 dB and 3 dB of SNR/sub seg/ improvement is achieved at a bit error rate of 3*10/sup -3/ and 3*10/sup -2/ respectively, over conventional CELP without channel coding.>

The authors introduce a novel approach to narrow- and medium-band speech coding that can dynamically balance the transmission rate between the excitation and the spectral parameters. The coding algorithm, called multimode coding, operates several coding blocks, each of which has a different bit assignment in parallel, and selects the optimum coding block frame by frame based on an evaluation of the reproduced speech quality. This coding algorithm is applied to 4.8 and 8.0 kb/s CELP coders, and 2.0-2.4 dB of SNRseg improvement is achieved over conventional CELP coders. The spectral distortion measure is added as an evaluation function, improving the subjective speech quality.>

A new 8 kbps speech coding algorithm called TC-MQ (time domain compression ADPCM-MQ) is proposed. It is based on time scale modification and sub-band coding with the aid of ADPCM with a multiquantizer. For time scale modification, the decimation/interpolation technique is introduced for the unvoiced period. Furthermore, in order to get computational accuracy of the pitch extraction for the voiced period, a method using the normalized autocovariance function is proposed. The algorithm was confirmed by computer simulations. The segmental SNR was about 13-16 dB for Japanese short sentences. A good mean opinion score value was also obtained by means of a subjective evaluation test.>

Hardware implementation aspects of sophisticated speech codecs are addressed. The major points discussed are approaches to implementation of the sophisticated speech codecs, requirements for DSP (digital signal-processing) implementation of the codecs, such as the type of arithmetic processing and the necessity of bit-level specifications, and codec implementation and DSP programming techniques for three specific coding algorithms: 32-kb/s ADPCM (adaptive digital pulse code modulation), 64-kb/s (7 kHz) SB (subband)-ADPCM, and 16-kb/s APC-AB (adaptive predictive coding with adaptive but allocation) codecs.>

A speech coding algorithm with low complexity and a short processing delay is introduced. The proposed algorithm is ADPCM (adaptive digital pulse code modulation) with a multiquantizer (ADPCM-MQ). The input signal is processed in parallel by multiple ADPCM coders with different characteristics. Then the optimum ADPCM coder with minimum error power is dynamically selected for each frame. A 16-kb/s codec based on this algorithm has been implemented using two general-purpose digital signal processors (MB8764) with 8.3 ms of total processing delay. A segmental SNR of 19-21 dB was achieved at 16 kb/s; with postfiltering the segmental SNR was increased to 23-25 dB. Combined with the time domain compression scheme, the algorithm can be easily applied to 8-kb/s coding. It is also extensible to variable-rate coding.>

This paper describes an implementation of a new 16 kbps speech codec using commercially available DSPs and its performance. The coding algorithm chosen here is ADPCM with Multi-Quantizer (ADPCM-MQ) which selects the optimum ADPCM coder frame by frame and switches to it dynamically. To implement this coding algorithm, we used two Fujitsu DSPs (MB8764), 1.5 chips for the encoder and 0.5 chip for the decoder. Reconstructed speech with a 21 dB segmental SNR was obtained. With error correction, this codec provides good speech quality even with a bit-error rate of 10^-2 to 10^-3. To improve the subjective quality of the reconstructed speech, adaptive postfiltering was also applied. Since the processing delay of this codec is less than 10 ms, no echo-canceller is needed. Moreover, 2400 bps voice band data (CCITT Rec.V. 26) could be transmitted with a data error rate from 10^-7 to 5×10^-6, and G.III facsimiles were successfully transmitted using this codec.

This paper describes a hardware architecture of an adaptive transversal filter with long delay taps and its LSI implementation. We developed an adaptive transversal filter VLSI with 512 taps which is suitable for an echo canceller system. We developed a new compuatational method suitable for VLSI implementation, and clarified the required computation accuracy and dynamic range by computer simulation. We built proto-type four channel echo canceller system using four VLSI chips and a sigle chip of general purpose digital signal processor.

Adaptive differential PCM (ADPCM) is an effective coding scheme to simplify the hardware and shorten the processing delay to realize a high-efficiency speech codec. The ADPCM with Multi-Quantizer (ADPCM-MQ) coding has been proposed as one of the highly efficient coding methods. In the ADPCM-MQ codec several ADPCM coding blocks with different quantization step-size update rates are operated in parallel, and the quantizer that gives the best characteristics is found and selected dynamically for each frame. This paper describes a new 8 to 9.6 kbps ADPCM-MQ coding algorithm that includes tree coding to improve the per-sample quantizing characteristic, and sub-band coding with high frequency band reconstruction to realize a lower bit rate coding. Computer simulation indicates good quality for speech reproduced by this algorithm with a segmental signal-to-noise ratio of 14 to 15 dB. Adaptive postfiltering can be added to enhance the subjective characteristics of the reproduced speech.

Recently much intensive research of 16kbps Speech coding algorithm has been conducted aiming to reduce the transmission bit rate and yet provides high speech quality. Adaptive predictive coding with adaptive bit allocation (APC-AB)[1] is considered to be one promising approach. However, the processing of this coding algorithm is so complicated that the implementation of the algorithm on a general-purpose signal processor, especially if fixed-point arithmetic DSPs are used, requires careful study of arithmetic operation precision and same way to reduce the number of processing cycles. Taking account of these points, real-time signal processing using a fixed-point signal processing chip (FDSP-3) has been studied, and a prototype codec has been realized. The prototype codec satisfied the CCITT mask of signal-to-total distortion ratio for PCM codecs and showed quality good enough for "toll" speech.

This paper describes a newly developed CMOS LSI DSP and its application to a 32 Kbps ADPCM CODEC and a 4,800 bps data MODEM. The paper first analizes the required memory capacities of ROM and RAM as a function of arithmatic operation capability of DSP. Based on the results, the LSI DSP is developed, which has a proper amount of memory capacities. It has a multiplier which operates at a rate of 1.4 M operations/s. It is also equipped with a versatile I/O interface circuit which is suitable for multi-processors configuration of a system.

This paper describes a fast data processing LSI unit tailored to the digital signal processing (DSP) applications in the field of electrical communications. The results of successful application to the 4800 bit/s modem are also given. The LSI processor discussed here adopts a firmware control scheme to enhance the flexibility and freedom of application and extensively utilizes the pipeline processing technique to attain high speed data handling capability. The various operations encountered in DSP systems are unified into one operation of the typeA \times B + C \rightarrow Dand the LSI processor is designed to continuously perform this operation, while the data to be operated are transferred sequentially into the processor controlled by exterior firmware. The developed LSI handles 8 bit data at the clock frequency of 1.152 MHz and manages 144 K operations per second (6.9 μs cycle time). The LSI is an N-MOS chip containing 1500 gates and packaged in a 40 pin DIP. The automatic equalizer for 4800 bit/s modem was implemented using two of the developed LSI processors and about 4 K ROM and 1 K RAM memory chips. The measurement on this modem gave the error rate of 10-5atS/N = 17.6dB and error free phase jitter allowance of 55° p-p. Application of the LSI processor to digital filters for roll-off spectrum shaping and timing signal extraction is also described.