FPGA interconnection network is implemented using nMOS pass transistor multiplexers. Since the threshold voltage drop across an nMOS device degrades the high logic value, the pMOS transistors of the downstream buffers do not turn fully off, making this approach suffer from static power consumption due to the short-circuit currents and reduced noise margins. The standard pMOS transistor pull-up in the active feedback of an inverter reduces the static power consumption but degrades the switching time and/or dynamic power consumption. We propose to use capacitive boosting to increase the gate voltage of the pass transistors, thus driving the multiplexer output to the full high voltage level at a faster rate than the pMOS pull-up can alone. This way, the signal transitions are accelerated and the short-circuit current of downstream buffers are cut off. The simulations carried out with Cadence indicate a reduction of at least 10% in propagation delay for the proposed circuit versus the standard one across 180nm, 130nm, 90nm, and 65nm technologies.

This study compares the speed, area, and latency of shift-and-add arithmetic implemented within fine-grained FPGA resources and within a proposed coarse-grained embedded block for FPGAs. It begins by optimizing the mapping of various shift-and-add architectures within the fine-grained resources of a commercial FPGA to determine which provides the best area, delay, and latency for various word-lengths. It then proposes a new coarse-grained block that supports 16, 32, and 64-bit shift-and-add arithmetic and finally compares coarse-grained implementations to the best fine-grained implementations. Our results show that the coarse-grain implementations are between 15 and 47 times smaller and 5 to 18 times faster, depending on the implementation.

Increasing the symbol rate up to 25% faster than the Nyquist criteria for a digital communications system with QPSK modulation with an AWGN channel does not significantly increase the bit error rate or required transmission bandwidth. This so-called Faster-than-Nyquist (FTN) signalling has not been used in commercially deployed communications systems since the previously proposed implementation schemes required large receiver complexity. This paper introduces a reformulation of FTN signalling in terms of a non-square matrix multiplied by a sample vector of modulated QPSK symbols. It is shown that with this formulation the receiver complexity to detect the transmitted data for an AWGN channel is well within the complexity bounds for standard digital communication systems. This formulation enables an analysis of FTN signalling directly comparing it to standard higher order modulation and data coding techniques.

Prior work has developed a variation of MCCDMA, block-spread OFDM (BSOFDM), providing good error performance over stationary channels with low detection cost and allowing parallel computation to reduce the receiver latency. The previous detection algorithms developed for BSOFDM are not robust to fast fading. In this paper, it is demonstrated through the use of performance bounds that the performance degradation under fast fading is caused by limitations of the previous decoding algorithms, and is not an inherent limitation of BSOFDM. A novel iterative detection algorithm is introduced with intrinsic data-level parallelism for detecting BSOFDM in the presence of fast fading. Detection is first performed independently on subblocks of the received block vector. Information is exchanged between these parallel detectors in an iterative manner by estimating the interference between the blocks and removing it from the signal vector. It is shown that the computational complexity of this algorithm is not significantly higher than the prior detection algorithms for BSOFDM, and achieves excellent BER for fast fading with fixed-point arithmetic, making it suitable for use on embedded systems. In addition the inherent parallelism of this algorithm means multiple computational units can be exploited, if available, to reduce receiver latency.

The long-word and very long-word addition required in cryptography applications generally requires custom hardware support provided by ASICs or application-specific instructions in ASIPs. As an alternative to these expensive solutions, FPGAs have been used. To reduce the overhead of commercial FPGAs in implementing cryptography, CryptoRA, a cryptographically-oriented reconfigurable array, has recently been proposed. This paper presents a circuit level implementation of the CryptoRA array which provides the following results: (i) a speed-up of 1.15times to 2.1times from the LUT output to a fast-addition carry path, (ii) a speed-up greater than 1.2times for long-word addition and subtraction, and (iii) these results come at a cost of only an additional 2.5% of a computing tile's silicon area.

Expanding transcendental functions in a series of Shift-and-Add operations is an alternative to Taylor or Chebyshev series expansions when fixed-point arithmetic with reduced wordlength is required. Typically, reconfigurable arrays do not provide architectural support for shift operations. Instead, shift operations are emulated by either multiplexing logic or multiplication by a power of 2. In this paper we describe the architecture of a reconfigurable array that can natively support shift operations. Rather than augmenting the reconfigurable fabric with dedicated shift units, the interconnection network is extended with shift capabilities. This is conceptually possible since a shift operation is a rearrangement and not a combination of the signals. Layers of computing tiles supporting Shift-and-Add/Subtract and Add-and-Select operations are interleaved with interconnect layers. On such a reconfigurable array, a variety of transcendental functions can be efficiently implemented.

We present a cryptography-oriented reconfigurable array called CryptoRA that efficiently supports very long-integer addition and subtraction. We first describe the CryptoRA architecture and show that extending the dedicated carry chains of modern FPGAs over the orthogonal direction, followed by merging two FPGA columns to create computing tiles that support both generate and propagate signals of a carry-lookahead network, provides a reduction in operation latency. Then, we show that splitting a tile's Look-Up Table into two halves provides additional benefits in terms of latency and flexibility in using the dedicated generate and propagate chains. According to our estimations, long-integer addition widely used in cryptography is more than 22% faster on CryptoRA than on Virtex-II Pro FPGA. This improvement has a large positive impact on implementing cryptography applications in embedded environments.

Software Defined Radios (SDRs) offer a programmable and dynamically reconfigurable method of reusing hardware to implement the physical layer processing of multiple communications systems. An SDR can dynamically change protocols and update communications systems over the air as a service provider allows. In this paper we present techniques for implementing communications systems in software. We describe briefly the SB3011 platform and programming environment. We then present a number of useful techniques that can be used to implement working systems. We further describe in which systems these techniques are implemented.

We describe the implementation of a coarse-grain reconflgurable array that implements shift operations within its interconnection network. The connection point of such an array is a triangular matrix of switches. The reconflgurable array is geared toward the implementation of sequential Shift-and- Add algorithms. We show that a triangular switch-box that uses a level-restoring buffer with an unfolded multiplexer exhibits improved propagation delay and power consumption against prior art. This leads to a coarse-grain reconflgurable array that efficiently implements transcendental functions.

Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the high logic value, causing the pMOS transistor of the downstream buffer to not turn fully off, this approach suffers from static power consumption and reduced noise margins. The standard pMOS transistor pull-up in an active feedback of an inverter reduces the static power consumption, but degrades the switching time and/or active power consumption. We propose a circuit technique to build level-restoring buffers, which improves the propagation delay or active power consumption at a tiny area penalty. Our main idea is to replicate the nMOS element of the downstream buffer, where each replica is driven by a signal that originates from earlier stages of the nMOS-tree multiplexer. This way, when passing high logic values, signals from earlier stages directly drive the downstream buffer improving the delay or the slope of the transition edge. The passing of low logic values is still performed in the original way by the nMOS tree and the pMOS element of the downstream buffer. The simulations indicate an average improvement of the composite metric area-delay-energy product of 25% versus the standard approach across 180 nm, 130 nm, and 90 nm technologies.

This paper presents a TriMedia processor extended with three reconfigurable designs for entropy decoding (ED), inverse quantization (IQ), and two-dimensional (2-D) inverse discrete cosine transform (IDCT), and assesses the performance gain that is provided by such extensions when performing MPEG2-compliant pel reconstruction. We first describe an extension of the TriMedia architecture, which consists of a multiple-context field programmable gate array (FPGA)-based reconfigurable functional unit (RFU), a configuration unit managing the reconfiguration of the RFU, and their associated instructions. Then, we address the computation of the ED, IQ, and 2-D IDCT tasks, and propose to provide reconfigurable hardware support for a variable-length decoder that can decode two symbols per call (VLD-2), an inverse quantizer that can dequantize four coefficients per call (IQ-4), and an 1-D IDCT (1-D IDCT). The most important aspects concerning the implementation of the FPGA-mapped VLD-2, IQ-4, and 1-D IDCT units, as well as the organization of the software routines calling these FPGA-mapped computing units are outlined. Experimental results indicate that by configuring each of the VLD-2, IQ-4, and 1-D IDCT units on a different FPGA context, and by activating the contexts as needed, the FPGA-augmented TriMedia can perform MPEG2-compliant pel reconstruction with an average speed-up of 1.4/spl times/ over the standard TriMedia.

A case study on color space conversion (CSC) for MPEG decoding, carried out on the FPGA-augmented TriMedia processor is presented. That is, a transform from Y'CbCr color space to R'G'B' color space is addressed. First, we outline the extension of TriMedia architecture consisting of FPGA-based reconfigurable functional units (RFU) and associated instructions. Then we analyse a CSC (RFU-specific) instruction which can process four pixels per call, and propose a scheme to implement the CSC operation on RFU(s). When mapped on an ACEX EP1K100 FPGA, the proposed CSC exhibits a latency of 10 and a recovery of 2 TriMedia@200 MHz cycles, and occupies 57% of the device. By configuring the CSC facility on the RFU(s) at application load-time, color space conversion can be computed on FPGA-augmented TriMedia with 40% speed-up over the standard TriMedia.

The paper presents a Design Space Exploration (DSE) experiment which has been carried out in order to determine the optimum FPGA-based Variable-Length Decoder (VLD) computing resource and its associated instructions, with respect to an entropy decoding task which is to be executed on the FPGA-augmented TriMedia/CPU64 processor We first outline the extension of the TriMedia/CPU64 architecture, which consists of an FPGA-based Reconfigurable Functional Unit (RFU) and the associated generic instructions. Then we address entropy decoding and propose a strategy to partially break the data dependency related to variable-length decoding. Three VLDs (VLD-1, VLD-2, VLD-3) instructions which can return 1, 2, or 3 symbols, respectively, are subsequently analyzed. After completing the DSE, we determined that VLD-2 instruction leads to the most efficient entropy decoding in terms of instruction cycles and FPGA area. The FPGA-based implementation of the computing resource associated to VLD-2 instruction is subsequently presented. When mapped on an ACEX EP1K100 FPGA from Altera, VLD-2 exhibits a latency of 8 TriMedia cycles, and uses all the Electronic Array Blocks and 51% of the logic cells of the device. The simulation results indicate that the VLD-2-based entropy decoder is 43% faster than its pure software counterpart.

In this paper a parallel Variable-Length Decoding (VLD) scheme is introduced. The scheme is capable of decoding all the codewords in an N-bit buffer whose accumulated codelength is at most N. The proposed method partially breaks the recursive dependency related to the MPEG-2 VLD. All possible codewords in the buffer are detected in parallel and the sum of the codelengths is provided to the external shifter aligning the variable-length coded input stream for a new decoding cycle. Two length detection mechanisms are proposed: the first approach determines the length in a parallel/serial fashion and the second using a new device denoted as MultiplexedAdd. In order to prove feasibility and determine the limiting factors of our proposal, the parallel/serial codeword detector with 32-bit input has been described in behavioral non-optimized VHDL and mapped onto Altera's ACEX EP1K100 FPGA. The implemented prototype exhibits a latency of 110 ns and uses 32% of the logic cells of the device. When applied to MPEG-2 standard benchmark scenes, on average 3.5 symbols are decoded per cycle.

This paper describes an experiment which aims to reveal the potential impact on performance yielded by augmenting a TriMedia-CPU64 processor with a multiple-context FPGA core. We first propose an extension of the TriMedia CPU64 architecture, which consists of a reconfigurable functional unit and its associated instructions. Then, we address the decoding of variable-length codes on such extended TriMedia and describe the architecture and FPGA-implementation of a variable-length decoder (VLD) computing facility. When mapped on an ACEX EP1K100 FPGA, the proposed VLD exhibits a latency of 7 cycles. Preliminary results indicate that by configuring each of the VLD and 1-D IDCT (which is described elsewhere) facilities on a different FPGA context, and by activating the contexts as needed, the augmented TriMedia can perform macroblock parsing followed up by pel reconstruction with an improvement of 20 - 25% over the standard TriMedia.

A new group-delay based spectral domain is explored for representation of speech signals and for extraction of robust features. The spectrum is computed using the group-delay functions defined on the autocorrelation of a short segment of speech. The features derived from this spectrum are easy to compute and are robust to the background noise. The invariance of the spectral shape to noise in this domain is demonstrated by comparing the group-delay spectrum to the Discrete Fourier transform (DFT) based spectrum and the LPC-derived spectrum. The new domain representation can be applied for parameter estimation as well as speech recognition. In this paper we present preliminary results of using such features in Speaker-Dependent (SD) as well Speaker-Independent (SI) recognition systems.