To verify the logical correctness of communication protocols, protocol verification should be invoked in the design phase. In this paper, we propose a new communicating finite state machine (CFSM)-based verification method, which is called reverse protocol verification. By analyzing the properties of deadlock error, unspecified reception error and channel overflow error, some candidate erroneous global states are generated. Then, each candidate global state is checked whether there is a path, i.e. a global state sequence, which can connect to the original initial global state. If there is a path, then the candidate global state is really an erroneous global state and the protocol under designing does have some logical errors; alternatively, if there is no candidate global state or none of the candidate global states has a path, then the protocol is error free. Based on the reverse method, an incremental protocol specification system (IPSS) has been developed on SUN SPARC workstations. Usage and applications of IPSS are also presented in this paper.

The extended communication finite state machine (ECFSM) model, which belongs to the state transition model, has been used to formally specify protocols with context variables and predicates. Global state reachability analysis is one of the most straight-forward ways to verify communication protocols specified in the state transition model. Many CFSM-based global state reduction techniques have been proposed to reduce the complexity of global state reachability analysis. However, these reduction techniques cannot be directly applied to ISO's Estelle and CCITT's SDL, which are ECFSM-based formal description techniques (FDTs)-based protocol verification systems. Based on Itoh and Ichikawa's (1983) CFSM-based, Chu and Liu's (1989) ECFSM-based reduction techniques, and Huang et al.'s (1990) CFSM-based incremental verification technique, this paper proposes a protocol verification technique for ECFSM-based n-entity protocols. In this way, the integrated reduced incremental verification technique can be directly applied to Estelle or SDL -based protocol verification systems.>

Formal description techniques (FDTs) provide formal and abstract ways to specify what protocols have to do and what the features of the protocols need. Protocol verification is a process for detecting logical errors, such as deadlock, unspecified receptions, and channel overflow errors, in communication protocols. Estelle is a FDT defined by the International Organization for Standardization (ISO) for protocol specifications. The authors present an incremental protocol verification technique and an Estelle interpreter which accepts Estelle protocol specifications for incremental protocol verification.>