As fabrication technology moves to 100 nm and below, profound nanometer effects become critical in developing silicon chips with hundreds of millions of transistors. Both EDA suppliers and system houses have been re- tooling, and new methodologies have been emerging. Will these efforts meet the challenges of nanometer silicon such as performance closure, power, reliability, manufacturability, and cost? Which aspects of nanometer design are, or are not, under control? This session will consist of a debate between two teams of distinguished representatives from EDA suppliers and system design houses. Which side has the right answers and roadmap? You and a panel of judges will decide!

An interdisciplinary multilaboratory effort to develop an implantable neural prosthetic that can coexist and bidirectionally communicate with living brain tissue is described. Although the final achievement of such such a goal is many years in the future, it is proposed that the path to an implantable prosthetic is now definable, allowing the problem to be solved in a rational, incremental manner. Outlined in this report is our collective progress in developing the underlying science and technology that will enable the functions of specific brain damaged regions to be replaced by multichip modules consisting of novel hybrid analog/digital microchips. The component microchips are "neurocomputational" incorporating experimentally based mathematical models of the nonlinear dynamic and adaptive properties of biological neurons and neural networks. The hardware developed to date, although limited in capacity, can perform computations supporting cognitive functions such as pattern recognition, but more generally will support any brain function for which there is sufficient experimental information. To allow the "neurocomputational" multichip module to communicate with existing brain tissue, another novel microcircuitry element has been developed-silicon-based multielectrode arrays that are "neuromorphic," i.e., designed to conform to the region-specific cytoarchitecture of the brain, When the "neurocomputational" and "neuromorphic" components are fully integrated, our vision is that the resulting prosthetic, after intracranial implantation, will receive electrical impulses from targeted subregions of the the brain, process the information using the hardware model of that brain region, and communicate back to the functioning brain. The proposed prosthetic microchips also have been designed with parameters that can be optimized after implantation, allowing each prosthetic to adapt to a particular user/patient.

Low-power low-voltage mixed-analog/digital-signal CMOS technology is used in implementing a novel dynamic-synapse neural network microchip. A basic building block for dynamic process is implemented with a variable current source, resistors, charging/discharging capacitances, and transmission gates. It was designed and simulated in 0.35 /spl mu/m technology. The dynamic synapse function is implemented with resistor-capacitor exponential circuits, analog summing circuit, voltage comparator with hysteresis, and digital logic block. A neural network system with six input neurons, two output neurons, and 18 synapses is designed. Each neuron and dynamic synapse has individual threshold and gain. The circuit was simulated with two different input pulses to evaluate feedback inhibitory pulses, each action potential, and EPSP (excitatory post synaptic potential) of each dynamic processing point. Simulation results show that this dynamic synapse can be used for advanced neural processing including speech recognition application.

A unified approach for the MOS transistor drain current modeling through all the operation regions is presented. Instead of the direct sum approach, the proposed use of interpolation and sigmoid functions can unify the drain current expression including the drift and diffusion components for the weak- and strong-inversion regions. This approach results in a differentiable continuity in conductances with respect to the gate, drain, and bulk bias voltages. As verified by the experimental data, the model shows an accurate prediction capability for the transconductance and output conductance characteristics in both strong- and weak-inversion regions.

A low power smart vision system based on a large format (currently 1 K/spl times/1 K) active pixel sensor (APS) integrated with a programmable neural processor for fast vision applications is presented. The concept of building a low power smart vision system is demonstrated by a system design which is composed with an APS sensor, a smart image window handler, and a neural processor. The paper also shows that it is feasible to put the whole smart vision system into a single chip in a standard CMOS technology. This smart vision system on-a-chip can take the combined advantages of the optics and electronics to achieve ultra-high-speed smart sensory information processing and analysis at the focal plane. The proposed system will enable many applications including robotics and machine vision, guidance and navigation, automotive applications, and consumer electronics. Future applications will also include scientific sensors such as those suitable for highly integrated imaging systems used in NASA deep space and planetary spacecraft.

The code division multiple access (CDMA) scheme has become very popular due to high efficiency for spectrum usage and robust jamming resistance. However, the inherent near-far problem is an impediment. Though deliberate power control algorithms can partially handle this problem, the cost is high. Under the assumption of synchronous symbols and white Gaussian noise, a neural-network-based detector with robust near-far resistance is presented. By proper mapping and applying a hardware annealing technique, compact realization of high precision detectors is possible.

Rapid progresses in computers, telecommunication, and consumer electronics research have stimulated the emergence of powerful multimedia systems that will have profound impacts, on scientific, industrial, business endeavors, and even our daily lives. Continuous advances in deep-submicron microelectronic fabrication technologies have made possible the integration of millions of transistors on a single silicon microchip. However, one of the anticipated major technological breakthroughs will be the efficient and reliable use of optical links to increase the communication bandwidth and quality of electronic systems. Optical links can be used not only at the machine-to-machine level, but also at the board-to-board and chip-to-chip levels. The architecture, design, and associated measurement results are presented regarding the use of optical interconnections to enhance desktop multimedia computing systems.

A compact neural network receiver to process code division multiple access (CDMA) communication is presented. In CDMA system, near-far problem is a major impediment for the performance of a conventional detector. By using a compact neural network with hardware annealing function and combinatorial optimization technique, an optimal multiuser detector can be implemented. The algorithm and architecture of the compact neural network based CDMA receiver are described.

An engineering annealing method for optimal solutions of cellular neural networks is presented. Cellular neural networks are very promising in solving many scientific problems in image processing, pattern recognition, and optimization by the use of stored program with predetermined templates. Hardware annealing, which is a paralleled version of mean-field annealing in analog networks, is a highly efficient method of finding optimal solutions of cellular neural networks. It does not require any stochastic procedure and henceforth can be very fast. The generalized energy function of the network is first increased by reducing the voltage gain of each neuron. Then, the hardware annealing searches for the globally minimum energy state by continuously increasing the gain of neurons. The process of global optimization by the proposed annealing can be described by the eigenvalue problems in the time-varying dynamic system. In typical nonoptimization problems, it also provides enough stimulation to frozen neurons caused by ill-conditioned initial states.

Paralleled array processors based on cellular neural networks (CNNs) are very useful in high-speed, real-time signal and image processing because of its simplicity for problem mapping and high potential computational bandwidth. Local interconnection and simple synaptic operators are the most attractive features of the cellular neural network (CNN) for VLSI implementation. A computing architecture for CNN processing engine which can be applied for several challenging VLSI hardware design problems, such as CNN accelerator design for heterogeneous computing, is presented. This continuous-time CNN processing engine with digital-programmable synapses and flexible digital interface is designed and prototyped using the current-mode CMOS circuits. A prototyping 5/spl times/5 array processor chip is designed and fabricated in 2.0 /spl mu/m CMOS technology. Measurement results of this prototype chip and its building blocks for array processor design are presented. Experimental results of edge detection operation of this prototype chip are also given.

A smart-pixel cellular neural network with hardware annealing capability, digitally programmable synaptic weights, and multisensor parallel interface has been under development for advanced space sensor applications. The smart-pixel CNN architecture is a programmable multi-dimensional array of optoelectronic neurons which are locally connected with their local neurons and associated active-pixel sensors. Integration of the neuroprocessor in each processor node of a scalable multiprocessor system offers orders-of-magnitude computing performance enhancements for on-board real-time intelligent multisensor processing and control tasks of advanced small satellites. The smart-pixel CNN operation theory, architecture, design and implementation, and system applications are investigated in detail. The VLSI implementation feasibility was illustrated by a prototype smart-pixel 5/spl times/5-neuroprocessor array chip of active dimensions 1380 /spl mu/m/spl times/746 /spl mu/m in a 2-/spl mu/m CMOS technology.

VLSI neural networks can speed up the computation and signal processing by many orders of magnitude through compact, low-power parallel processing. Key microsystem design issues are critically addressed for successful industrial and scientific applications.

A cellular neural network (CNN) is a locally connected, massively paralleled computing system with simple synaptic operators so that it is very suitable for VLSI implementation in real-time, high-speed applications. VLSI architecture of a continuous-time shift-invariant CNN with digitally-programmable operators and optical inputs is proposed. Circuits with annealing ability are included to achieve optimal solutions for many selected applications.

The hardware annealing method is effective on finding the optimal solutions for selected cellular neural network applications. The method is presented and analyzed in terms of the generalized energy which corresponds to the cost function in optimization problems. The network stability property and parameters in annealed neural networks are described to serve as a guideline for practical applications.

The output of a multi-level neuron produces a multibit representation. The total network size with multilevel neurons can therefore be significantly reduced from a conventional network with two-level neurons. The reduction in network size benefits VLSI implementation. Due to the nonlinearity associated with a neuron transfer function, multiple local minima exist in the energy function of a multi-level analog-to-digital decision network. The procedure for applying hardware annealing by continuously changing the neuron gain from a low value to a certain high value, to reach the globally optimal solution is described. Several simulation results are also presented. The parallel hardware annealing method is much faster than the simulated annealing method on digital computers.>

The BSIM plus MOS transistor model is developed for accurate and efficient analysis and simulation of submicron VLSI circuits. A compact parameter set is created to achieve high accuracy and continuity of the drain current and its derivatives in the subthreshold, triode and saturation regions of operation. Experimental results on individual transistors from deep submicron technologies are presented. Benchmark tests are performed to illustrate the salient features of the BSIM plus model.>

Back-propagation neural networks with Gaussian function synapses have a better convergence property over those with linear-multiplying synapses. A compact analog Gaussian synapse cell which is not biased in the subthreshold region has been designed for fully-parallel operation. This cell can approximate a Gaussian function with accuracy around 98% in the ideal case. Device mismatch induced by fabrication process will cause some degradation to this approximation. Programmability of the proposed Gaussian synapse cell is achieved by changing the stored synapse weight W/sub ji/, the reference current and the sizes of transistors in the differential pair.>

The BSIM plus MOS transistor model is developed for simulation of digital and analog VLSI circuits in advanced submicron technologies. A compact parameter set is carefully selected to accurately characterize transistors and achieve continuity of the drain current and its derivatives across the different regions of operation. Several submicron modeling techniques are described. Simulated results agree well with measured data of transistors from two industrial technologies.>

A self-organization neural network architecture is used to implement vector quantization for image compression. A modified self-organization algorithm, which is based on the frequency-sensitive cost function and centroid learning rule, is utilized to construct the codebooks. Performances of this frequency-sensitive self-organization network and a conventional algorithm for vector quantization are compared. The proposed method is quite efficient and can achieve near-optimal results. Good adaptivity for different statistics of source data can also be achieved.>

The VLSI architecture for an adaptive vector quantizer is presented. The adaptive vector quantization method does not require a-priori knowledge of the source statistics and the pre-trained codebook. The codebook is generated on the fly and is constantly updated to capture local textual features of data. The source data are directly compressed without requiring the generation of codebook in a separate pass. The adaptive method is based on backward adaption without any side information. The speed of data compression by using the proposed adaptive method is much faster than that by using the conventional vector quantization methods. The algorithm is shown to reach the rate distortion function for memoryless sources. In image processing, most smooth regions are matched by the code vectors and most edge data are preserved by using the block-data interpolation scheme. The VLSI architecture consists of two move-to-front vector quantizers and an index generator. It explores parallelism in the direction of the codebook size and pipelining in the direction of the vector dimension. According to the circuit simulations using the popular SPICE program, the computation power of the move-to-front vector quantizer can reach 40 billion operations per second at a system clock of 100 MHz by using 0.8 /spl mu/m CMOS technology. It can provide a computing capability of 50 Mpixels per second for high-speed image compression. The proposed algorithm and architecture can lead to the development of a high-speed image compressor with great local adaptivity, minimized complexity, and fairly good compression ratio.>

Back-propagation neural networks with Gaussian function synapses have better convergence property over those with linear-multiplying synapses. In digital simulation, more computing time is spent on Gaussian function evaluation. We present a compact analog synapse cell which is not biased in the subthreshold region for fully-parallel operation. This cell can approximate a Gaussian function with accuracy around 98% in the ideal case. Device mismatch induced by fabrication process will cause some degradation to this approximation. The Gaussian synapse cell can also be used in unsupervised learning. Programmability of the proposed Gaussian synapse cell is achieved by changing the stored synapse weight W/sub ji/, the reference current and the sizes of transistors in the differential pair.>

A high-speed image compression VLSI processor based on the systolic architecture of difference-codebook binary tree-searched vector quantization has been developed to meet the increasing demands on large-volume data communication and storage requirements. Simulation results show that this design is applicable to many types of image data and capable of producing good reconstructed data quality at high compression ratios. Various design aspects of the binary tree-searched vector quantizer including the algorithm, architecture, and detailed functional design are thoroughly investigated for VLSI implementation. An 8-level difference-codebook binary tree-searched vector quantizer can be implemented on a custom VLSI chip that includes a systolic array of eight identical processors and a hierarchical memory of eight subcodebook memory banks. The total transistor count is about 300000 and the die size is about 8.67/spl times/7.72 mm/sup 2/ in a 1.0 /spl mu/m CMOS technology. The throughput rate of this high-speed VLSI compression system is approximately 25 Mpixels per second and its equivalent computation power is 600 million instructions per second.>

An analog VLSI neural network processor was designed and fabricated for communication receiver applications. It does not require prior estimation of the channel characteristics. A powerful channel equalizer was implemented with this processor chip configured as a four-layered perceptron network. The compact synapse cell is realized with an enhanced wide-range Gilbert multiplier circuit. The output neuron consists of a linear current-to-voltage converter and a sigmoid function generator with a controllable voltage gain. Network training is performed by the modified Kalman neuro-filtering algorithm to speed up the convergence process for intersymbol interference and white Gaussian noise communication channels. The learning process is done in the companion DSP board which also keeps the synapse weight for later use of the chip. The VLSI neural network processor chip occupies a silicon area of 4.6 mmx6.8 mm and was fabricated in a 2-mum double-polysilicon CMOS technology. System analysis and experimental results are presented.

Three basic neural network schemes have been extensively studied by researchers: the iterative networks, the backpropagation networks, and the self-organizing networks. Simulated annealing is a probabilistic hill-climbing technique that accepts, with a nonzero but gradually decreasing probability, deterioration in the cost function of the optimization problems. Hardware annealing, which combines the simulated annealing technique with continuous-time electronic neural networks by changing the voltage gain of neurons, is discussed. The initial and final voltage gains for applying hardware annealing to Hopfield data-conversion networks are presented. In hardware annealing, the voltage gain of output neurons is increased from an initial low value to a final high value in a continuous fashion which helps to achieve the optimal solution for an optimization problem in one annealing cycle. Experimental results on the transfer function and transient response of electronic neural networks achieving the global minimum are also presented.

The system design of a locally connected competitive neural network for video motion detection is presented. The motion information from a sequence of image data can be determined through a two-dimensional multiprocessor array in which each processing element consists of an analog neuroprocessor. Massively parallel neurocomputing is done by compact and efficient neuroprocessors. Local data transfer between the neuroprocessors is performed by using an analog point-to-point interconnection scheme. To maintain strong signal strength over the whole system, global data communication between the host computer and neuroprocessors is carried out in a digital common bus. A mixed-signal very large scale integration (VLSI) neural chip that includes multiple neuroprocessors for fast video motion detection has been developed. Measured results of the programmable synapse, and winner-takes-all circuitry are presented. Based on the measurement data, system-level analysis on a sequence of real-world images was conducted.

An adaptive method for lossy data compression and the associated VLSI architecture have been developed. This scheme does not require a-priori knowledge of the source statistics and codebook training. The codebook is generated on the fly and is constantly updated to capture local textual features of data. The algorithm is proven to reach rate distortion function for memoryless sources. The authors also propose a computing architecture which consists of a vector quantizer and an encoded-data generator. By using this method, a high-speed VLSI processor with good local adaptivity, less complexity and fair compression ratio can be achieved.>

Architecture and custom circuit design of a multiprocessor chip for digital signal processing (DSP) and digital image processing have been developed. Mappings of digital image processing and neural network algorithms are presented. The processor design supports the execution of key signal processing functions. The processing elements can be connected in a 1D linear ring or 2D systolic mesh array. A microprogrammed controller is used to enhance the processor performance. Each processor occupies 4.1 mm/sup 2/ by using an industrial-scale 0.5- mu m CMOS technology from TRW Inc. Sixty-four processing elements can be implemented in a 1.5-cm*1.8-cm chip and achieve 2.56 billion calculations per second.>

A self-organization neural network architecture is used to implement the vector quantizer for image compression. A modified self-organization algorithm, which is based on the frequency upper-threshold and centroid learning rule, is utilized for constructing the codebooks. The performances of the self-organization network and the conventional algorithm for vector quantization are compared. This algorithm yields near-optimal results and is computationally efficient. The self-organization network approach is suitable for adaptive vector quantizers. The self-organization network approach uses massively parallel computing structures and is very promising for VLSI implementation.>

An analog systolic architecture that uses multiple neuroprocessors for image restoration is presented. For a two-dimensional image, parallel processing is performed for different rows of pixel data and pipelined processing is performed on each row of pixel data. For the image restoration neuroprocessor, local data computation is executed by analog circuitry to achieve full parallelism and to minimize power dissipation. Interprocessor communication is carried out in the digital format to maintain strong signal strength across the chip boundary and to allow multichip operation for high-speed image processing.>

An adaptive electronic neural network processor has been developed for high-speed image compression based on a frequency-sensitive self-organization algorithm. The performance of this self-organization network and that of a conventional algorithm for vector quantization are compared. The proposed method is quite efficient and can achieve near-optimal results. The neural network processor includes a pipelined codebook generator and a paralleled vector quantizer, which obtains a time complexity O(1) for each quantization vector. A mixed-signal design technique with analog circuitry to perform neural computation and digital circuitry to process multiple-bit address information are used. A prototype chip for a 25-D adaptive vector quantizer of 64 code words was designed, fabricated, and tested. It occupies a silicon area of 4.6 mmx6.8 mm in a 2.0 mum scalable CMOS technology and provides a computing capability as high as 3.2 billion connections/s. The experimental results for the chip and the winner-take-all circuit test structure are presented.

A trainable VLSI neuroprocessor for adaptive vector quantization based upon the frequency-sensitive competitive learning algorithm has been developed for high-speed high-ratio image compression applications. Simulation results show that such an algorithm is capable of producing good-quality reconstructed image at compression ratios of more than 20. This design includes a fully parallel vector quantizer and a pipelined codebook generator which obtains a time complexity O(1) for each quantization vector. A 5*5-dimensional vector quantizer prototype chip has been designed, fabricated and tested. It contains 64 inner-product neural units and an extendable winner-take-all block. This mixed-signal chip occupies a compact Si area of 4.6*6.8 mm/sup 2/ in 2.0- mu m scalable CMOS technology.>

A locally connected multi-layer stochastic neural network and its associated VLSI array neuroprocessors have been developed for high-performance image flow computing systems. An extendable VLSI neural chip has been designed with a silicon area of 4.6*6.8 mm/sup 2/ in a MOSIS 2 mu m scalable CMOS process. The mixed analog-digital design techniques are utilized to achieve compact and programmable synapses with gain-adjustable neurons and winner-take-all cells for massively parallel neural computation. Hardware annealing through the control of the neurons' gain helps to efficiently search the optimal solutions. Computing of image flow using one 2 mu m 72-neuron neural chip can be accelerated by a factor of 187 more than a Sun-4/260 workstation. Real-time image flow processing on industrial images is practical using an extended array of VLSI neural chips. Actual examples on moving trucks are presented.>

An adaptive VLSI neuroprocessor based on vector quantization algorithm has been developed for real-time high-ratio image compression applications. This VLSI neural-network-based vector quantization (NNVQ) module combines a fully parallel vector quantizer with a pipelined codebook generator for a broad area of data compression applications. The NNVQ module is capable of producing good-quality reconstructed data at high compression ratios more than 20. The vector quantizer chip has been designed, fabricated, and tested. It contains 64 inner-product neural units and a high-speed extendable winner-take-all block. This mixed-signal chip occupies a compact silicon area of 4.6*6.8 mm/sup 2/ in a 2.0- mu m scalable CMOS technology. The throughput rate of the 2- mu m NNVQ module is 2 million vectors per second and its equivalent computation power is 3.33 billion connections per second.>

A GaAs gigahertz optical receiver module was designed and fabricated through a MESFET technology. Design techniques were used to increase the bandwidth of the receiver circuit. Basic digital circuits were also fabricated to extract technology parameters and to provide information for higher levels of integration. This receiver and the associated laser diode based transmitter are suitable for integrated optoelectronic signal processing and optical neurocomputing.>

A systematic approach to test analog array-processor neural chips is presented. Unique testing problems for analog neural chips are described and effective solutions are discussed. Based on the hierarchical methodology, testing of analog array-processor neural chips can be systematically addressed. The test results for programmable analog neural chips fabricated by a 2- mu m CMOS process are presented. These chips contain 25 neurons and 1600 synapses.>

Due to the rugged energy function of the original Hopfield networks, the output is usually one local minimum in the energy function. An analysis on the locations of local minima in Hopfield networks is presented, and a modified network architecture to eliminate such local minima is described. In particular, another amplifier is introduced at the processor nodes to give correction terms. This modified Hopfield network has been successfully applied to the construction of analog-to-digital converters with optimal solutions. Experimental results on the voltage transfer characteristics of data converters are presented.

A systematic approach to automatic layout generation for the emerging mixed analog-digital VLSI neural systems is described. A macro-cell layout methodology based on a hierarchical floorplanning and placement procedure, a constraint-driven analog module generator, and a priority-based block router have been exclusively developed for neural chip implementation. Special analog VLSI layout constraints are analyzed and properly incorporated into the layout generation on each level of the circuit hierarchy to achieve both high performance and overall area efficiency. The floorplans for single-layer fully-connected Hopfield neural chips and multiple-layer neural chips have been developed. Experimental results on a 16-neuron neural circuit are presented.>

The multilayer stochastic neural network and its associated VLSI array neuroprocessors are presented for VLSI optical flow computing. This network is well-suited to VLSI implementation due to the high parallelism and local connectivity. Instead of using deterministic scheme, a stochastic decision rule implemented with electronic annealing techniques is used to search optimal solutions. VLSI array neuroprocessor architecture is proved to be an effective supercomputing hardware for real-time optical flow applications. A prototype 25-neuron chip for this VLSI array neuroprocessors (called a velocity-selective hyperneuron chip) has been implemented using MOSIS 2- mu m CMOS technology. A real-time optical flow machine is feasible by using arrays of hyperneuron chips.>

Real-time digital image restoration using massively parallel Hopfield neural chips is presented. An efficient mixed-signal VLSI design with analog circuitry to perform neural computation and digital circuitry to process multiple-bit pixel information greatly reduces the network size. Analog programmable synapse cells of 8 bit accuracy are dynamically refreshed. The gain-adjustable neurons enable electronic annealing to quickly reach global minimum in energy function. A prototype 25-neuron chip occupies a silicon area of 4.6*6.8 mm/sup 2/ in MOSIS 2- mu m CMOS process has been designed and tested. The speedup factor for each chip is 90 compared to the Sun-3 workstation. An 100-neuron image-restoration chip is achievable in the industrial-level 1- mu m technologies.>

A VLSI neural network with concurrent network retrieving and learning processes is described. Weightings of analog synapse cells are externally programmed and require dynamic refreshing. Gain-adjustable neurons are used to facilitate electronic annealing to efficiently search for an optimal solution. Two prototype chips which operate in a synchronous fashion and an asynchronous fashion, respectively, were fabricated and tested. The 25-neuron chip for image restoration occupies a silicon area of 4.6×6.8 mm2in a MOSIS 2-μm CMOS process and achieves 300×speedup compared with a Sun-3/60 workstation. If implemented in industrial-level 1-μm VLSI technologies, a fully connected general-purpose neural chip with 500 neurons can be achieved in a 1-cm2silicon area

A tool for the smart layout of analog modules, which aims to provide a flexible analog layout solution for the mixed analog-digital VLSI design environment, is described. New algorithms have been developed for novel primitive cell recognition, intelligent layout and detail routing, and performance-driven optimization. Software implementation and experimental results on several analog VLSI modules such as operational amplifiers and voltage-controlled oscillators are presented.>

A novel approach to the design of digital and analog VLSI with built-in reliability is presented. Physics-based reliability models for key failure mechanisms in VLSI circuits are used to achieve accurate and efficient circuit-level reliability prediction and improvement. A prototype integrated-circuit reliability simulator (RELY) and experimental results on hot-carrier damage and metal electromigration effects are presented.>

An accurate and efficient temperature modeling methodology for the semiempirical BSIM (Berkeley short-channel IGFET model) has been developed for MOS VLSI circuit simulation. A sensitive model parameter subset which has large effects on transistor output characteristics is determined from the sensitivity analysis. Updating of model parameter values for this sensitive subset is performed prior to circuit simulation at each given temperature. For a 1.2 mu m CMOS process, the sensitive subset for temperature effects consists of only eight out of the 67 BSIM parameters. Circuit simulation using this sensitive subset approach to predict temperature effects has shown good agreement with experimental data on transistor output characteristics, inverter transfer characteristics, and oscillation frequency of a 31-stage ring oscillator.>

A prototype knowledge-based analog-circuit synthesis system is presented. An expert system has been developed to act as a design assistant in an iterative analog design process. Design flexibility is greatly enhanced by adopting the self-reconstructing technique for the flexible architecture approach. Being able to recognize critical nodes and circuit primitives, the layout generator is capable of generating compact layouts with special analog layout considerations. An expert system for assisting the design of a two-stage CMOS operation amplifier, CAMP, and a layout generator for circuit layout generations, LAMP, have been developed for the expert-system-based analog IC design automation environment. Experimental results are shown to demonstrate the capabilities of the system.>

The development of an MOS transistor charge and capacitance model for the analysis and design of VLSI circuits is described. The total stored charge in each of the gate, bulk, and channel regions is obtained by integrating the distributed charge densities over the thin-oxide area. Charge conservation is guaranteed in this model by using the terminal charges as the state variables. The capacitance expressions have the nonreciprocal property. Partition of channel charge into the drain and source components is 40/60 in the saturation region. In the triode region, this partition changes asymptotically to 50/50 as the gate voltage increases. The carrier-velocity saturation effect is incorporated through both the modification of channel quasi-Fermi level and the determination of drain saturation voltage. Implementation of the model in the SPICE circuit simulator has been achieved. Modeled results compare well with experimental data for transistors with channel lengths as small as 0.75 mu m.>

MOSGEN, a program that provides efficient interface between the device simulator, PISCES and the circuit simulator SPICE, is described. Algorithms to generate parameters for SPICE built-in MOS transistor models have been developed and incorporated into MOSGEN. Only six PISCES simulation results are required to generate a complete set of SPICE parameters. This interface program, together with SUPREM, PISCES, and SPICE, form an integrated simulation environment for VLSI design. Such an integrated simulation environment facilitates the designers to examine just how a microscopic fabrication variable, such as implantation dose, affects final device and circuit performance as well as product yield.>

Precise determination of transistor electrical parameters is essential for accurate circuit simulation. The strong geometric dependences of MOS transistor electrical parameters can be modeled by the inverse-geometry formula. However, special care is needed in using the inverse-geometry formula. To prevent the short-channel and narrow-width effects being adversely mirrored to the drain-current evaluation of large transistors, we propose to clamp the dependences of transistor electrical parameters on small-geometry effects at a boundary (L /sub CLP/, W /sub CLP/). In principle three transistors with two different channel lengths and two different channel widths are required to extract the geometric dependence of various electric parameters. Our analysis shows that a set of five test transistors can increase the extraction accuracy by a factor of two, and thus is a better choice when both the modeling accuracy and test clip complexity are considered.