There has been significant interest in cellular systems employing direct sequence (DS) code division multiple access (CDMA), with no synchronization requirement between base stations (BS), especially in the context of the so-called third-generation (3G) wireless systems. In this case, since neighboring BSs use different spreading sequences, the mobile must first determine the spreading sequence being used by the BS(s) from which the mobile receives sufficiently strong signals. To facilitate acquisition, the total set of spreading sequences is divided into groups, and the group identification is transmitted over a synchronization channel. This paper describes a novel mechanism for transmitting the group identification (ID) using cyclically permutable (CP) codes; this scheme results in significant reduction in the search space, allowing for rapid acquisition. The technique described is currently a component of the radio access technology in the 3G partnership project (3GPP) proposal to the International Telecommunications Union (ITU) for 3G wireless systems (IMT-2000). An analysis of the three-stage search process required for acquisition and cell search is also presented, and simulation results are shown to demonstrate the efficacy of this approach.

There has been significant interest in cellular systems employing direct sequence CDMA, with no synchronization requirement between base-stations (BS), especially in the context of the so-called third generation wireless systems. In this case, since neighboring BS use different spreading sequences, the mobile must first determine the spreading sequence being used by the base station(s) from which the mobile receives sufficiently strong signals. To facilitate acquisition, the total set of spreading sequences is divided into groups, and the group identification is transmitted over a synchronization channel. This paper describes a novel mechanism for transmitting the group ID using cyclically permutable (CP) codes; this scheme results in significant reduction in the search space, allowing for rapid acquisition. The technique described is currently a component of the ARIB and ETSI proposals to the ITU, for third generation wireless systems (IMT-2000).

This paper presents a discussion of a top-down VLSI design approach which involves system level performance modeling, block level cycle based simulation, RTL/VHDL simulation and gate level emulation. An MPEG-2 audio/video decoder design example illustrates the use of this top-down approach. Most of the discussion concentrates on the concept of block level cycle based (BLCB) simulation. HW/SW co-design also played an important role in this work and our approach towards such co-design is discussed as well.

This paper deals with the system-level performance analysis and optimization of a class of digital systems we call mixed asynchronous-synchronous systems. In such a system, each computation module is either synchronous or asynchronous. The communication among all of the modules is assumed to be data driven. In order to adequately describe the timing of such architectures, we introduce a graph model called MASS, which is based on several extensions of timed marked graphs. The first extension is that the node set V is partitioned into synchronous and asynchronous nodes. A synchronous node can only fire at ticks of its local module clock. Based on these extensions, we analyze the behavior of MASS, in particular, period, periodicity, and maximal throughput rate. Finally, we introduce the optimization problem of assigning appropriate clock phases to synchronous nodes so to maximize the throughput rate of the resulting system. An exact solution as well as a polynomial time algorithm for nearly optimal phase assignment are presented.

Resynchronization is a post-optimization for static multiprocessor schedules in which extraneous synchronization operations are introduced in such a way that the number of original synchronizations that consequently become redundant significantly exceeds the number of additional synchronizations. Redundant synchronizations are synchronization operations whose corresponding sequencing requirements are enforced completely by other synchronizations in the system. The amount of run-time overhead required for synchronization can be reduced significantly by eliminating redundant synchronizations. However, since additional serialization is imposed by the new synchronizations resynchronization can produce significant increase in latency. This paper addresses the problem of computing an optimal resynchronization (one that results in the lowest average rate at which synchronization operations have to be performed) among all resynchronizations that do not increase the latency beyond a prespecified upper bound L/sub max/. Our study is based on the context of self-timed execution of iterative data flow programs, which is an implementation model that has been applied extensively for digital signal processing systems.

Synchronization overhead can significantly degrade performance in embedded multiprocessor systems. This paper develops techniques to determine a minimal set of processor synchronizations that are essential for correct execution in an embedded multiprocessor implementation. Our study is based in the context of self-timed execution of iterative dataflow programs; dataflow programming in this form has been applied extensively, particularly in the context of signal processing software. Self-timed execution refers to a combined compile-time/run-time scheduling strategy in which processors synchronize with one another only based on inter-processor communication requirements, and thus, synchronization of processors at the end of each loop iteration does not generally occur. We introduce a new graph-theoretic framework, based on a data structure called the synchronization graph, for analyzing and optimizing synchronization overhead in self-timed, iterative dataflow programs. We also present an optimization that involves converting a synchronization graph that is not strongly connected into a strongly connected graph.