Haruo Kato

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3ranked-venue papers

2as first author

0since 2021 · last 1992

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

1 paper

Electronic design automation · 91% Integrated circuit design · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
Electronic design automation › physical design › placement and routing gate array layout	1	1985	Automatic layout algorithms for function blocks of CMOS gate arrays · DAC 1985
Electronic design automation physical design	1	1985	Automatic layout algorithms for function blocks of CMOS gate arrays · DAC 1985
Electronic design automation › physical design placement and routing	1	1985	Automatic layout algorithms for function blocks of CMOS gate arrays · DAC 1985
Integrated circuit design › ASIC design CMOS gate array	1	1985	Automatic layout algorithms for function blocks of CMOS gate arrays · DAC 1985

Methods — techniques the papers use, named apart from their topics

automatic layout algorithm · 0.0

Year	Publication	Venue	Position
1992	CCD Image Sensor Test Using Cellular Automation-Type Pattern Recognition System abstract This paper describes an automatic method for detecting color sensitivity errors in CCD image sensors. The technique, based on interpreting spatio-temporal transient signals, provides results that correlate well with manual test methods. Haruo Kato	ITC	1
1990	Color reproduction test for CCD image sensors abstract A color reproduction test algorithm for CCD (charge-coupled-device) color image sensors has been developed. It quantifies color reproduction errors using white balanced images obtained by the CCD. In determining manufacturer-specific parameters, relative color sensitivity as a function of hue and pattern recognition sensitivity depending on position are obtained from the visual classification test by the test personnel. The test algorithm can easily implement these functions, and thus behaves, its behavior is similar to that of the visual test by the test personnel. The quantification is a good representation of human visual tests; a correlation coefficient of 0.8718 was attained.> Haruo Kato	ITC	1
1985	Automatic layout algorithms for function blocks of CMOS gate arrays abstract Automatic layout algorithms, placement and routing, for function blocks of CMOS gate arrays are presented. Shigeo Noda, Hitoshi Yoshizawa, Etsuko Fukuda, Haruo Kato, Hiroshi Kawanishi, Takashi Fujii	DAC	4