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Wen-Jun Hsu

dblp:01/4178 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1993
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test		 0.011993
Design of Pseudoexhaustive Testable PLA with Low Overhead · IEEE Trans. Computers 1993
Electronic design automation › hardware verification and test › VLSI testing
programmable logic array testing		 0.011993
Design of Pseudoexhaustive Testable PLA with Low Overhead · IEEE Trans. Computers 1993
Electronic design automation › hardware verification and test › test generation
pseudoexhaustive testing		 0.011993
Design of Pseudoexhaustive Testable PLA with Low Overhead · IEEE Trans. Computers 1993
Electronic design automation › hardware verification and test
test generation		 0.011993
Design of Pseudoexhaustive Testable PLA with Low Overhead · IEEE Trans. Computers 1993
Electronic design automation
logic synthesis		 0.011992
Coalgebraic Division for Multilevel Logic Synthesis · DAC 1992
Electronic design automation › logic synthesis
multilevel logic synthesis		 0.011992
Coalgebraic Division for Multilevel Logic Synthesis · DAC 1992

Methods — techniques the papers use, named apart from their topics

partitioning algorithm · 0.0coalgebra · 0.0
YearPublicationVenuePosition
1993 Design of Pseudoexhaustive Testable PLA with Low Overhead
abstract
The pseudoexhaustive testing (PET) scheme is an economical approach to testing a large embedded programmable logic array (PLA). The authors propose an efficient algorithm named low overhead PET (LOPET) to partition the product lines. By applying this algorithm, both the area overhead and test length are reduced significantly.>
Wen-Zen Shen, Gwo-Haur Hwang, Wen-Jun Hsu, Yun-Jung Jan
 IEEE Trans. Computers3
1992 Coalgebraic Division for Multilevel Logic Synthesis
Wen-Jun Hsu, Wen-Zen Shen
 DAC1