Interconnects are sophisticated in a multi-die IC using integration technology such as interposer or Wafer-Level Packaging (WLP), and thus they could become vulnerable to early lifetime failure or aging. Our previous work in [12] provides a way to monitor the delay of a TSV non-intrusively by a transition time binning procedure. However, it is not suitable for longer interconnects in an interposer or in the Re-Distribution Layer (RDL) of a WLP-packaged IC, as the cost could become prohibitively high due to large area overhead. To overcome this limitation, we propose a new scheme in this paper by incorporating a Distributed Time-to-Digital Converter (d-TDC). Experimental results indicate that such a scheme can support on-line delay monitoring for long interconnects, while having an area overhead equivalent to 2 boundary scan cells only for each interconnect.

Die-to-die interconnects linking multiple functional dies in a modern 3-D or 2.5-D IC by micro-bumps could experience resistance increase after certain time of field operation due to parametric defects or aging. To cope with this reliability threat, we present an “on-line transition-time binning method” that aims to continuously detect excessive transition time occurring at a target die-to-die interconnect. Our method attaches a monitor to the termination end of each target interconnect. Any transition (rising or falling) is converted into a pulse-width first, which is then further compared to a dynamically tunable threshold for a binary pass/fail judgment. By multiple runs of transition-time monitoring while sweeping the threshold incrementally, the “transition-time bin” of each target interconnect can be derived and thereby a timing failure threat can be detected by a monitor center before it actually strikes.

A faulty interposer in a 2.5-D integrated circuit often results in a hefty loss as the potentially expensive known-good-dies bonded on the interposer will have to be discarded as well. To avoid such a last-minute loss during a multichip integration process, built-in self-repair (BISR) is highly valuable. Even though there have been many BISR schemes in the literature, the proposed method offers a number of distinct features. First, it can target not only catastrophic faults, but also timing faults. Second, it can be applied to general multi-pin interconnects and it can be applied to repair an interposer with multiple faulty interconnects. Third, it can perform the test-and-then-repair flow on-the-fly, and thereby eliminating the overhead of extra repair storage incurred in previous methods.

A fractional-N frequency synthesizer for IEEE 802.11a/b/g standard with the design focused on voltage controlled oscillator (VCO) is proposed in this paper. Unlike the traditional approach of tuning VCO oscillation frequencies by capacitive varactors, the proposed VCO with a voltage-controlled inductor, which is made by an integrated transformer technology, is adopted. A digital delta-sigma modulator realized with FPGA verification is employed for fractional-N purpose to meet IEEE 802.11a/b/g channels. The frequency synthesizer is simulated in 0.18-/spl mu/m CMOS process with a loop-bandwidth of 300 KHz for a 32-MHz reference and the power dissipation is about 40 mW from a 1.8-V supply.

In this paper, a burst-mode clock and data recovery (CDR) circuit using a 1/4-rate clock technique is realized for optical communication system. The CDR circuit contains a phase detector and a muxed-oscillator to control the phase of the clocks. In-lock operation is accomplished on the first data transition, and after the first data the clocks are in phase for all data until the data transition is over. The CDR circuit is implemented with 0.18-/spl mu/m CMOS technology. The experimental results show that the proposed CDR circuit recover the incoming 1.8-Gb/s data.