Large scale sensor networks are non trivial to deploy due to their heterogeneous, distributed nature. This paper presents a technique to configure and deploy sensor applications on heterogeneous networks that is based on the use of virtual filesystem abstractions. The approach can augment existing sensor software build procedures with the ability to configure and deploy software, all using the filesystem framework. The paper presents an architecture to implement the idea and illustrates its use by means of a prototype. Automation of the configuration and deployment processes by use of scripting based techniques implemented using the filesystem abstractions is described.

Hardware compilers for high-level programming languages are important tools to reduce the design productivity gap in hardware development. In this paper a hardware compilation approach is described, which is able to generate a hardware description based on a specification in a high-level programming language such as ANSI C. No modification of the program specification is required, allowing it to be suitable for a hardware and a software implementation at the same time. The parallelism is extracted by using VLIW optimization techniques. The generated hardware implementation is an instance-specific VLIW core, which is defined by its high-level program specification. To demonstrate the principle of the design flow, a prototype is presented which uses the VEX compiler as the front-end and the Handel-C tool chain as the back-end. The resulting instance-specific VLIW cores of several test functions are compared to equivalent software implementations.

This paper presents the architectural design of a reconfigurable and extensible very long instruction word (VLIW) processor. In addition to architectural extensibility, our processor also supports reconfigurable operations. Furthermore, we present an application development framework to optimally exploit the freedom of reconfigurable operations. Because our processor is based on the VEX ISA, we already have a good compiler which is able to deal with ISA extensibility and reconfigurable operations. Our results show that different configurations of our processor lead to considerable cycle count reductions for a selected benchmark application.

This paper describes a reconfigurable architecture based on field-programmable gate-array (FPGA) technology for monitoring and analyzing network traffic at increasingly high network data rates. Our approach maps the performance-critical tasks of packet classification and flow monitoring into reconfigurable hardware, such that multiple flows can be processed in parallel. We explore the scalability of our system, showing that it can support flows at multi-gigabit rate; this is faster than most software-based solutions where acceptable data rates are typically no more than 100 million bits per second.

We present a scalable architectural approach which aims to simplify embedded software development by supporting key development tasks like debugging, tracing and monitoring. Our approach uses file system interfaces to represent various entities in the embedded system hierarchy that are merged and exported to clients using a messaging protocol. Unlike many JTAG based debug solutions, ours is compositional and supports heterogeneous, concurrent debugging.

Lx is a scalable and customizable VLIW processor technology platform designed by Hewlett-Packard and STMicroelectronics that allows variations in instruction issue width, the number and capabilities of structures and the processor instruction set. For Lx we developed the architecture and software from the beginning to support both scalability (variable numbers of identical processing resources) and customizability (special purpose resources). In this paper we consider the following issues. When is customization or scaling beneficial? How can one determine the right degree of customization or scaling for a particular application domain? What architectural compromises were made in the Lx project to contain the complexity inherent in a customizable and scalable processor family? The experiments described in the paper show that specialization for an application domain is effective, yielding large gains in price/performance ratio. We also show how scaling machine resources scales performance, although not uniformly across all applications. Finally we show that customization on an application-by-application basis is today still very dangerous and much remains to be done for it to become a viable solution.

Abstract We have previously developed a verified algorithm for compiling programs written in an occam-like language into delay-insensitive circuits. In this paper we show how to retarget our compiler for clocked circuits. Since verifying a hardware compiler is a huge effort, it is significant that we are able to retarget our compiler proof without recreating that effort. The chief contribution of this paper is the methodology used for retargeting our compiler which is based upon a new model for systems with both synchronous and asynchronous behaviour. The retargeting proof utilizes both theorems proved algebraically by hand and theorems proved automatically by state exploration. The technique of protocol conversion is used extensively in modularizing the proof of the clocked implementation.

We present a novel approach to prototyping asynchronous circuits which uses clocked field programmable gate arrays (FPGAs). Unlike other proposed techniques for implementing asynchronous circuits on FPGAs, our method does not attempt to preserve the pure asynchronous nature of the circuit. Rather, it preserves the communication behavior of the circuits and uses synchronous duals for common asynchronous modules.

We present a compiler, debugger, linker, and hardware/software interface for data acquisition systems based on hardware that is reconfigurable by the end user. Unlike earlier work, we choose a source language which is software-oriented. Our goal is to make systems with reconfigurable hardware accessible to scientists and engineers who are competent programmers but are not hardware literate.

Abstract We show how to retarget a compiler for occam-like programs from generating two-phase delay-insensitive circuits to generating four-phase speed independent circuits. The specifications of the two-phase circuit elements for our compiler are used to produce a set of equivalent specifications for four-phase circuit elements using a set of protocol converters. Automatic tools have been used in checking that our four-phase implementations satisfy their specifications.