An experimental recognition system for tabular data is described. It recognizes vertical and horizontal lines and, if they form tabular data, it analyzes the tabular structure. The paper proposes a new method to extract dotted lines that allows few, if any, recognition errors. It also describes a new data structure for tabular data that is easily combined with character recognition, which consists of rectangles and their labels. The line and table recognition methods described here is characterized by the fact that it only entails scanning the image array once. Some experimental results are also discussed.

This paper presents a signature analysis method that achieves a minimum aliasing rate. A fault stay map derived from exact fault simulation without fault dropping indicates whether a fault remains in an output data compressor at each time step. The fault stay map is used to determine the timing of multiple signature observations to achieve the minimum aliasing rate under certain constraints. Experimental results for some combinational circuits modeled on a single stuck-at fault are presented. They show that only two signature observations are required to achieve 0% aliasing in almost all circuits.>

An experimental business card recognition system is described that recognizes Japanese business cards of a wide variety both in formats and fonts. It also classifies recognition results into several predefined categories so that a business card database is built automatically. The overall procedure divides into a character recognition phase and a linguistic processing phase. In the first phase, the system gives a strictly local approach toward line segmentation to cope with slanted images. In the linguistic processing phase, recognition result strings generated in the former phase are analysed, classified and verified with the help of built databases. Some experimental results are also discussed.>

This paper presents a sequential circuit fault simulation method using a Fault Information Tracing algorithm (FIT). FIT handles information which represents how faults on each line propagate to fault convergence gates. By tracing the information backward from primary output, the fault detectability is directly determined. This technique drastically reduces fault effect propagation, achieves precise results, and is applicable to single and multiple stuck-at faults. One of the problems in sequential circuit fault simulation with analytical methods is how to deal with the multiple fault effect which is caused by faults stored in storage elements. Sequential circuit fault simulation by FIT is accomplished by executing multiple fault analysis. The algorithm was implemented in C, and results for ISCAS'89 benchmark circuits are presented.

A fault simulation method called the fault information tracing (FIT) algorithm is presented. Although the basic concept is similar to that of the critical path tracing (CPT) method, which traces sensitive inputs backward to directly determine the fault detectability, FIT is a multiple fault propagation method which considers propagation of all possible stuck-at faults between a gate input and output. Moreover, FIT manages a 'fault information flag' which represents both fault detectability and circuit topology between the current line and a primary output. Use of the fault information flag makes it possible to greatly reduce reconvergent fanout stem analysis. Consequently, exact and efficient simulation is achieved with near linear time complexity. The FIT algorithm is described and results are presented. In addition, the FIT procedure consists of simple propagation of fault information flags between logic gates, which enable implementation on parallel processors. Its suitability for parallel processors. Its suitability for parallel processing is discussed. Moreover, a parallel fault simulation method for AAP2, a massively parallel processor system containing 65536 processing elements, is described.>

A highly integrated array processor (AAP2)-LSI has been developed. After the past 3 years study on the adaptive array processor 1 (AAP1), a challenging improvements on the SIMD's restraints are achieved by using the AAP2-LSI. The AAP2 array system makes it possible to carry out wideband modifiable operation (pseudo MIMD). Furthermore, each PE is capable of supporting a large amount of memory. The AAP2 potential for massively, parallel and pipelined processing is discussed in the field of image processing and CAD applications. A highly integrated array processor (AAP2)-LSI has been developed. After the past 3 years study on the adaptive array processor 1 (AAP1), a challenging improvements on the SIMD's restraints are achieved by using the AAP2-LSI. The AAP2 array system makes it possible to carry out wideband modifiable operation (pseudo MIMD). Furthermore, each PE is capable of supporting a large amount of memory. The AAP2 potential for massively, parallel and pipelined processing is discussed in the field of image processing and CAD applications.