VLDB 2026 Research / reviewers in the wild / expert
Cary K. Chin
dblp:01/6644
· DBLP profile ↗
3ranked-venue papers
2as first author
0since 2021 · last 1987
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
0.0 | 2 | 1987 | Pseudorandom Testing · IEEE Trans. Computers 1987 Test Length for Pseudorandom Testing · IEEE Trans. Computers 1987 |
Electronic design automation › hardware verification and test › random testing
pseudorandom testing |
0.0 | 2 | 1987 | Pseudorandom Testing · IEEE Trans. Computers 1987 Test Length for Pseudorandom Testing · IEEE Trans. Computers 1987 |
Electronic design automation › hardware verification and test
test generation |
0.0 | 1 | 1987 | Pseudorandom Testing · IEEE Trans. Computers 1987 |
Electronic design automation › hardware verification and test › design for testability
built-in self-test |
0.0 | 1 | 1987 | Test Length for Pseudorandom Testing · IEEE Trans. Computers 1987 |
Electronic design automation › hardware verification and test
fault coverage |
0.0 | 1 | 1987 | Pseudorandom Testing · IEEE Trans. Computers 1987 |
Methods — techniques the papers use, named apart from their topics
random sampling without replacement model · 0.0linear feedback shift register · 0.0detectability profile analysis · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1987 | Test Length for Pseudorandom TestingabstractThe process of determining the required test length for a desired level of confidence for pseudorandom testing using a random sampling without replacement model is examined. The differences between random and pseudorandom testing are discussed and developed. The strictly random testing model is shown to be inaccurate for high confidence testing of combinational circuits. A method of calculating the required test length for pseudorandom testing based upon fault detectabilities is described. The result provides a very accurate prediction of required test length applicable to self-test using pseudorandom inputs. Cary K. Chin, Edward J. McCluskey |
IEEE Trans. Computers | 1 |
| 1987 | Pseudorandom TestingabstractAlgorithmic test generation for high fault coverage is an expensive and time-consuming process. As an alternative, circuits can be tested by applying pseudorandom patterns generated by a linear feedback shift register (LFSR). Although no fault simulation is needed, analysis of pseudorandom testing requires the circuit detectability profile. Kenneth D. Wagner, Cary K. Chin, Edward J. McCluskey |
IEEE Trans. Computers | 2 |
| 1985 | Test Length for Pseudo Random Testing
Cary K. Chin, Edward J. McCluskey |
ITC | 1 |