In this article, we propose a method for sizing an arbitrary combinational datapath to minimize its energy consumption. Our method involves deriving expressions for the components of energy consumption at both the stage and path levels. In this work, we identify overshoot energy ($E_{\text {OS}}$) consumption as a previously unreported component contributing to energy consumption, particularly significant in the near/sub-threshold voltage regime. We determine that this$E_{\text {OS}}$consumption is proportional to the input and output transition times and size of a logic gate at a particular stage of a datapath. We also observe that, for a given number of stages (N) and path effort, the total energy consumption is optimized when the stage effort (f) in a datapath is kept constant. Based on our observations and derivations of all the energy components and the requirement for a constant “f” in the datapath, we develop a method to minimize the energies of a logic circuit while maintaining the timing closure requirement. We determine that the non-critical paths (NCPs) must be sized to a minimum “f” while maintaining the timing requirements. We verified our models on several ISCAS and EPFL benchmark circuits with an average reduction of 28.1% (41.2%) and 19.2% (28.4%) in energy consumption [figure of merit (FoM)], respectively. The proposed methodology predicts the total energy consumption at a stage and path level of N-stage logic, with only one-time SPICE simulation on a single stage, with a maximum error of 1.3% and 1.62%, respectively, against SPICE simulations. The simulations are performed in Synopsys HSPICE environment with ST Microelectronics 65 nm CMOS and 28 nm FDSOI technology nodes, resulting in a very good agreement with the developed methodology.

This manuscript proposes an SRAM-based hybrid analog compute-in-memory (CIM) architecture to enhance the signal margin. This hybrid architecture presents fully differential current-based and C-2C charge-sharing-based multiplication and accumulation (MAC) CIM schemes for 4-bit MAC operation. The MAC operation of the filter weight's least significant bits (w0and w1) is implemented in the current-based CIM. However, the MAC operation of the most significant bits (w2and w3) is implemented in the charge-based CIM. The proposed architecture achieves a 4.37× enhancement in signal margin compared to the state-of-the-art. The energy efficiency and throughput of the proposed architecture are 1551.5 TOPS/W and 512 GOPS, respectively, at 0.9 V supply voltage and 250 MHz frequency. A convolutional neural network (CNN) is implemented on the proposed architecture, and the inference accuracy for the MNIST and CIFAR-10 data sets is 98.6 % and 86 %, respectively. The proposed architecture is scalable for multi-bit MAC operation and implemented in 28 nm CMOS technology.

We propose switching activity factor-based effective current source model (SAFE) for aging-aware static timing analysis (STA), a new technique for estimating the timing performance of digital circuits. SAFE is based on the development of device-level variation-aware analytical timing models of stacked and multistage logic cells (commonly employed transistor topologies in a synthesized netlist of a random logic path), which drastically reduces the recharacterization efforts of the standard cells. The models developed are derived as a function of input transition time$(T_{R})$and load capacitance$(C_{L})$. The timing performance of a standard cell degrades with threshold voltage$(V_{\mathrm {th}})$degradation in a MOS device due to various aging mechanisms. SAFE, makes the entire STA process aging aware by updating its model coefficients with$V_{\mathrm {th}}$degradation caused by aging. It is achieved by proposing a method for estimating$V_{\mathrm {th}}$degradation under various stress conditions, including static, dynamic, and asymmetric, that applies to any process design kit (PDK). To consider asymmetric aging, we have developed a method to find effective switching activity factor$(\alpha _{\mathrm {eff}})$for N-stage stacked and N-stage parallel logic which is used to find the value of switching activity factor$(\alpha)$at intermediate nodes in pipelined logic circuits. Our simulations are performed in Mentor Graphics Eldo SPICE environment using STMicroelectronics 28 and 65-nm CMOS process. The proposed technique provides a high-simulation accuracy (2.5% average error) when compared with SPICE simulations. Finally, we achieved a ~98.14% reduction in the required number of simulations using SAFE when compared with a completely SPICE/Aging simulation-based approach.

This paper explains the impact of body biasing$\boldsymbol{V}_{\mathbf{BS}}$on the performance of the epitaxial layer-based SOl Line Tunnel FE Ts (L- TFE T). The drain current$(I_{\mathbf{D}})$increases with the reverse$V_{\text{BS}}$, and then saturates. This occurs as the occupancy probability and the band-to-band tunneling (BTBT) generation initially increase with the reverse body bias and remain unaltered from any further increase in$\boldsymbol{V}_{\mathbf{BS}}$. Therefore, the occupancy probability in the source valance band plays a vital role in determining the modulation of$\boldsymbol{I}_{\mathbf{D}}$with$\boldsymbol{V}_{\mathbf{BS}}$. The reverse$V_{\text{BS}}$at which the drain current attains a maximum is defined as$V_{\text{BSAT}}$, and it changes almost linearly with the gate bias$(V_{\text{GS}})$. We have proposed a novel physics-based model to investigate the dependence of$\boldsymbol{V}_{\mathbf{BSAT}}$‘ on$V_{\text{GS}}$. An increase of 40-60% in$\boldsymbol{V}_{\mathbf{D}}$with the reverse$\boldsymbol{V}_{\mathbf{BS}}$is also observed. Forward VBS modulates the value of BTBT generation and$\boldsymbol{I}_{\mathbf{D}}$to a small extent. An incremental change in subthreshold slope and OFF -current is observed for the target device. Further,$\boldsymbol{V}_{\mathbf{DSAT}}$slightly reduces with an increase in the reverse$V_{\text{BS}}$.

A static timing analysis (STA) methodology based on an effective current source model (ECSM) is proposed for the first time for estimating the aging-aware path-level timing performance and its impact on the logical effort of a CMOS inverter for digital timing closure in pre-stress and post-stress conditions. Degradation in the threshold voltage$(V_{\mathrm{ th}})$of PMOS occurs due to temporal variability mechanisms (aging), such as negative bias temperature instability, resulting in delay degradation of a standard cell. Therefore, we proposed a technique to make the STA process aware of this degradation by developing device-level variation aware (with aging) timing models of CMOS inverters to represent threshold-crossing points (TCPs) in an ECSM.libs file as a function of stress time ($t$). A device-level approach for$V_{\mathrm{ th}}$degradation into different aging conditions, such as static and dynamic, is developed for a given process design kit to update TCPs in a (.libs) file as a function of$t$. A python-based tool is being developed to estimate the path-level timing performance of digital circuits in pre- and post-stress conditions. Again, we developed a technique for relating the inverter’s logical effort with$t$to resize a near-critical path in pre-stress conditions for achieving digital timing closure in pre- and post-stress conditions. The verification and validation of the proposed model with different benchmark circuits are performed using a parasitic extracted netlist in the Eldo SPICE environment with the 65-nm CMOS process technology. Finally, our model reduces the number of SPICE/Stress simulations by 98.13% compared to the previously reported only simulation-based techniques.

In this work, we propose an energy-efficient 64$\times $ 64 compute-in-memory (CIM) SRAM macro using a 7T bit-cell in 65nm CMOS UMC PDK. It supports 4-bit inputs, 4-bit weights & 4-bit outputs and performs 4-bit MAC operations. It also supports multiple row activations performing 1024 4b$\times $4b multiply and accumulate (MAC) operations in one clock cycle. Inputs are realized by the number of pulses on the read wordline (RWL), which discharges read bitline (RBL) according to bitwise multiplication of weights & inputs. Outputs of 4 columns storing 4-bit weights are then combined via charge sharing to perform a binary-weighted average representing MAC operation, further quantized by a flash analog to digital converter (ADC) giving 4-bit output. The proposed CIM macro achieves an energy efficiency of 28.9 TOPS/W and throughput of 212.9 GOPS operating at supply voltage 1 V with a 2 GHz clock frequency.

The concept of leveraging the transient negative capacitance (TNC) effect in a ferroelectric (FE) is a relatively new addition to the field of nanoelectronics. Until now, there has been no comparison of organic and oxide FE-based metal-FE-metal (MFM) devices in harnessing the TNC effect. As a result, we introduce an external resistor-MFM(R-MFM) series circuit to investigate the role of organic and oxide FEs in harnessing the TNC effect at low supply voltages. The multidomain Ginzburg-Landau-Khalatnikov theory is used to model the FE materials in a technology computer-aided design environment. We show that: (i) organic FE-based R-MFM series circuit can harness the TNC effect at just 1 V whereas an oxide FE-based R-MFM series circuit cannot; (ii) the coercivity of an organic FE is 77.39% lower than its counterpart, oxide FE; (iii) the remanent polarization of an organic MFM (1.2$\mu$C/cm2) is very close to the channel charge density of a CMOS transistor (1.6$\mu$C/cm2) making it helpful in addressing capacitance matching issues in NC transistor; (iv) an organic FE-based R-MFM series circuit dissipates 78.89% less energy than an oxide FE-based R-MFM series circuit; (v) the TNC effect and time are justified by its dependence on R. Finally, this article suggests that an organic FE-based MFM could be used as a gate stack of any transistor to achieve sub-60 mV/decade switching energy, making it ideal for ultra-low voltage NC transistors.

In this paper, for the first time, the phase noise analysis of a Multi-loop Skew based Single Ended Oscillator (MSSROs) is derived and validated. Compared to the three stages of conventional ring oscillators (CROs), SDROs provide an equivalent oscillation frequency with improved phase noise with increasing stages. The primary distinction between these two designs (SDRO and three-stage CROs) is the inherent skew offset between the PMOS/NMOS gates caused by the unique connection. This skew offset is the fundamental cause of delay cell noise suppression; the SDROs have loosely coupled oscillators that run concurrently, forming multiple 3-stages of separately driven Ring Oscillators. As a result, a shaping function is derived in terms of skew offset, and simulating these with varying skew offset results in suppressing behavior. Additionally, we derived phase noise for a skew-based design and validated it in PDKs of 180nm and 65 nm. We plotted the thermal (flicker) noise contribution and found that increasing the number of stages leads to an approximately 1-2 dB reduction in phase noise while maintaining the same NMOS/PMOS size ratio. Finally, a 2-3 dB reduction in phase noise is achieved in MSSROs by incorporating the shaping function into phase noise equations.

In this paper, the observation of transient negative capacitance signature (NCS) in an organic ferroelectric gate stack (OFEGS) at minimum supply voltage (Vs) of ±0.5 V is investigated employing a well-calibrated Ginzburg-Landau-Khalatnikov (GLK) model in the environment of Sentaurus technology computer-aided design (STCAD). We observe an 88.62 to 94.76 % reduction in the average coercive voltage (Vc) of the proposed OFEGS, which is still a significant challenge for the conventional ferroelectric (FE) lead zirconate titanate. We study the resistor-OFEGS (RCofe) series network behaviors in response to a bipolar and unipolar triangular signal. Our findings prove that the presence of NCS is directly correlated with the FE polarization (FEP) switching and not because of any extrinsic defects in the system. The various impacts of Vs, GLK parameters, R, dipole switching resistivity (Rofe) variations on the NCS response are investigated. The proposed OFEGS can harness the NCS effect at ±0.5 V with minimum energy dissipation of 4.81 × 10-16J, a challenge for the oxide FE-based gate stacks. Calibrating R to the maximum limit, we can capture the S-shaped ideal Landau path where the NCS is maximum with a small deviation of about ±0.006 V at zero FEP. Finally, an OFEGS based Landau transistor is implemented, providing a minimum subthreshold swing (SSmin) of 38.21 mV/decade, which is 36.32 % lesser than the fundamental SSminlimitation of 60 mV/decade. Therefore, the proposed OFEGS with a minimum Vs and remanent polarization (Pr=3D 1.244 μC/cm2) could be used as a gate stack for designing sub-60 mV/decade transistor technology.

In this article, a variation-aware design methodology for high-performance MOS-varactor voltage-controlled ring oscillator (MV-VCRO) in near-threshold-voltage (NTV) regime is proposed. The MV-VCRO is suitable because it eliminates series-stack transistors and generates rail-to-rail swing. For the first time, delay-models for conventional, bulk-driven (BD), and dynamic-threshold (DT) MV-VCROs considering nonlinearity in NTV regime is presented using effective drive current ( Ieff) and MOS-varactor capacitance models. The proposed design methodology is intuitive and considers process-voltage-temperature (PVT) variations at an initial stage of the design for width-length optimization. The methodology is highly efficient and does not require performing time-consuming Monte-Carlo (MC) simulations at post-layout stages. Look-up tables (LUTs) for MOS-varactor average-capacitances, and Ieffare generated while considering the regions of device operation during MV-VCRO output-node transitions while extracting the model parameters from one-time simulations. This approach is physics/topology-based and is verified in HSPICE and Sentaurus 2-D-TCAD simulations using STM65nm and 32 nm, respectively. The Ieff-models predict the oscillation frequency ( fOSC) with an accuracy of 97%, 96%, 97% for conventional, BD, DT-MV-VCRO, respectively. Furthermore, our estimated LUT- Ieff-capacitance models account for the change in fOSC, tuning range, and voltage-controlled oscillator (VCO)-gain with PVT variations with an accuracy-efficiency of 96%-99% compared to MC simulations. Furthermore, using LUTs, phase-noise, power consumption, and layout-area optimization technique is presented for a particular fOSC. Finally, the design methodology ensures that the desired fOSCis within the “linear” range of the VCO's-gain due to statistical variation of Vth, VDD, etc. This ensures resilience to PVT variations for NTV-VCO in linear feedback systems.

Near-threshold voltage (NTV) digital VLSI circuits, though important, have their sequential elements vulnerable to soft errors. The critical charge for a single event upset for a D-latch depends on its fan-out load, supply voltage, and transistor level parameters. A SPICE simulation-based estimation of the critical charge is highly resource/time intensive. In this paper, we propose a physics-based semianalytical model to estimate the critical charge of a static D-latch as a function of its fan-out load, supply voltage, temperature, and transistor levels parameters. It can, therefore, be used while considering process voltage temperature (PVT) variations. The critical charge estimated by the model is in good agreement with SPECTER simulations with a maximum error of less than 3.4% employing STMicroelectronics 65-nm process design kit (PDK). We also validated the model at 32-nm technology node using technology computer-aided design (TCAD) mixed-mode simulations (a maximum error of less than 7.5% is observed). Using this model, we devise a methodology to estimate the critical charge using a few dc simulations and a single transient SPICE simulation for a given PDK. This is an end-to-end method to include an accurate estimation of the critical charge for latches in NTV standard cell library characterization.