Specialized Digital Signal Processors (DSPs), which can be found in a wide range of modern devices, play an important role in power-efficient, high-performance image processing. Applications including camera sensor post-processing and computer vision benefit from being (partially) mapped onto such DSPs. However, due to their specialized instruction sets and dependence on low-level code optimization, developing applications for DSPs is more time-consuming and error-prone than for general-purpose processors. Halide is a domain-specific language (DSL) that enables low-effort development of portable, high-performance imaging pipelines—a combination of qualities that is hard, if not impossible, to find among DSP programming models. We propose a set of extensions and modifications to Halide to generate code for DSP C compilers, focusing specifically on diverse SIMD target instruction sets and heterogeneous scratchpad memory hierarchies. We implement said techniques for a commercial DSP found in an Intel Image Processing Unit (IPU), demonstrating that this solution can be used to achieve performance within 20% of highly tuned, manually written C code, while leading to a reduction in code complexity. By comparing performance of Halide algorithms using our solution to results on CPU and GPU targets, we confirm the value of using DSP targets with Halide.

In Software Defined Radio (SDR), some or all of the physical layer functions are implemented by software. In this paper, we focus on the channel decoding part of SDR. We use Synchronous Data Flow (SDF) and Cyclo-Static Data Flow (CSDF) graphs to model channel decoding functions. We want to tackle the problem of scheduling a dynamic mix of multiple radios with throughput constraints on a multi-standard multi-channel channel decoder. The decoder consists of a Micro-Controller Unit (MCU) and several weakly programmable Hardware Units (HU) with internal states and very limited buffer sizes. Each HU has a Round Robin (RR) scheduler hosted on the MCU. To reduce scheduling overhead, RR schedules applications at coarse granularity. Due to limited buffer sizes, some tasks of an application are tightly coupled. We propose a so-called coupled scheduling policy, which is a relaxation of strict gang scheduling, to concurrently schedule these tasks. We propose a technique to model coupled scheduling in (C)SDF graphs. Under our scheduling policies, we also design an admission controller to guarantee the throughput requirements of running applications. To verify the approach, we have implemented a simulation system to run DVB-SH and DVB-T concurrently and independently.

This paper presents a hardware design for a scalable, high throughput, configurable LFSR. High throughput is achieved by producing L consecutive outputs per clock cycle with a clock cycle period that, for practical cases, increases only logarithmically with the block size L and the length of the register N. Flexibility is ensured by offering full reconfigurability of the generator polynomial within 1 clock cycle. At the heart of the design is a decomposition of the block-based state-update transition-matrix into two matrices, which enables an efficient implementation in terms of both latency and area. Potential target applications for this design include PN sequence generation in CDMA systems, BIST for VLSI circuits, CRC, encryption and error correction.