Abstract Advancements on the Internet of Things (IoT) have enabled the development of advanced monitoring systems that can track human behavior and vital signs in real-time, which can have a real impact in the way healthcare is provided. This paper presents a system implementation to monitor and analyze a subject's behavior changes over time using IoT, with the objective of detecting the impact of an inhibitor drug on the subject's activity levels. In this research we present a case study by which we showed it is possible to follow the effect of an anticholinergic drug by means of an unobtrusive IoT system. We have monitored the physical activity of a subject in his residence for seven consecutive months to study the effect of the inhibiting drug doses introduced at three known specific timestamps. Following, we compared our detection results for the subject’s physical activity change timestamps with the medical staff medication doses timestamps. Our results show that we can detect the physical activity change at close timestamps compared to those indicated by the medical staff.

The authors propose a layered bilinear filter structure, and study its performance in an adaptive echo cancellation framework for high speed data transmission with precoding. In their application, they mainly consider the reduced order situations where the number of coefficients used in the echo canceller is less than that in the echo path. Computer simulation results show that when the echo path shows significant nonlinearity the layered form is effective in improving the echo cancellation performance with reduced computational complexity. Using bilinear echo cancellation with a small number of coefficients, echo return loss enhancement (ERLE) over the linear case improves by about 15 dB at a signal-to-noise ratio of 30 dB.>

A parsimonious adaptive nonlinear filtering structure based on bilinear models is presented. A state-dependent embedding for developing nonlinear filters is presented. It is used to develop a computationally efficient bilinear adaptive filter which requires only local adaptation. Modularity and local connectivity make the structure amenable to VLSI implementation. In contrast to previous input-output pair (system identification) frameworks, an inverse filtering problem is considered where only output is observable. The adaptation is shown to be dependent on both past and present gradients.>

Lattice filters for prediction of polynomial autoregressive processes are presented. By exploiting the structure of the nonlinearity, a reduced complexity lattice filter is derived. Bispectral tests show that the filter is effective in removing nonlinear dependence.>

The evolution of single-chip digital signal-processor (DSP) architectures is discussed. It is argued that multiple arithmetic units and functionally enhanced arithmetic units are promising directions for further evolution of the datapath architecture. Candidate structures are defined, and the operation of popular DSP benchmarks on these structures is demonstrated.>

A custom VLSI architecture for implementing the CCITT G.722 64-kb/s (7-kHz) wideband audio coding standard is presented. By tailoring the architecture to the algorithm, an architecture was designed that is capable of processing a full duplex channel in less than 625 cycles. That is 71-73% less cycles than are required by the reported general-purpose DSP implementations. In a 1.5- mu technology with a 100-ns cycle time, it is estimated that the architecture would consume 95000 mL/sup 2/ of silicon and support two full duplex channels on a single chip. The authors wrote a behavioral simulation of the architecture and its implicit microcode. This simulates the architecture's behavior at the bit level. The simulation passes the CCITT G.722 test vectors, demonstrating that the implementation conforms to the standard.>

Virtually all numerical techniques for elementary function generation share the common property of avoiding multiplication by iteratively performing shift operations. However, with the advent of VLSI, multiplier economics are considerably less formidable than before. The author proposes combining multipliers with these multiplication-free algorithms to construct fast methods of elementary function generation. He demonstrates the idea by combining multipliers with the CORDIC algorithm to achieve fast vector rotation.>

The author generalizes T.C. Chen's (1972) convergence computation method to multidimensional quantities, resulting in a unified algorithm for elementary function generation of which CORDIC and convergence computation functions are special cases. The generalized convergence computation method (GCCM) provides a unified mathematical framework for generating elementary functions and reveals that CORDIC is also a convergence method in reality. The practical benefit of this unification is the fact that heretofore distinct methods can now be implemented in a single expandable hardware structure.>

Use of the CORDIC (COordinate Rotation DIgital Computer) algorithm has been proposed for signal processing applications, since it has been shown that many DSP algorithms are fundamentally described by generalized rotations. However, the iterative nature of CORDIC has diminished its utility in high-speed real-time signal processing applications. The authors propose an array architecture for VLSI implementation of the CORDIC algorithm that aims to circumvent this shortcoming. The size and speed of the structure is compared with those of array multiplier and array divider structures. It is shown that the array CORDIC, while consuming a larger absolute real estate than these other structures, provides a better speed/area tradeoff as well as a rich set of elementary functions.>

Systems modems intended for use in relatively large private networks are characterized by high performance, reliability and flexibility to support network management, and multiple modes of operation and user features. This paper describes a programmable digital signal processor which is teamed with a 16-bit microprocessor in a dual processor architecture satisfying the requirements of high-speed voiceband systems modems. The architecture of the two custom integrated circuits which form the basis of the signal processor is presented. This processor has novel arithmetic, data structure address generation, and program flow-control capabilities, which result in a high utilization of the arithmetic unit and a low program overhead for housekeeping tasks. Some of these features are illustrated by programming examples.

A VLSI (very large scale integration) chip set is presented that is based on the square root normalized ladder recursions developed by Lee and Morf [1]. It is shown that the equations are amenable to implementation using the so-called CORDIC (Coordinate Rotation Digital Computer) algorithms (see eq. [2]) because the time and order updates are easily representable as orthogonal transformations or rotations [7, 12]. An integrated implementation which exploits the concurrency of the ladder recursions together with possible hardware, speed and area tradeoffs are presented. The general applicability of the chip set to other signal processing tasks is demonstrated by showing that the discrete Fourier transform (DFT) is naturally suited to the architecture.