ldquoMore than Moorerdquo is becoming the password for these coming years. New steps to overcome technology limitations to diffuse, on the same die, different chips to have a complete system have been developed. This approach is called system in package (SiP), a way to have in a package dies of logic, analog, memory, passive components, etc., assembled to obtain a miniaturized board. SiP performances and limitations are here analyzed to understand advantages versus system on chip (SoC). This paper is a discussion about the main items that can lead to the choice of the right approach-SiP or SoC-before a system design start. Three persons attend to our virtual meeting: an SoC technology development manager, expert in microcontroller embedded memories and technology integration; an SiP analog radio-frequency design senior expert; and a moderator that designed embedded memories and now SiP, all involved to understand how to reach a tradeoff among these two approaches. Like for the Yin and Yang, symbol of the equilibrium for the Taoist philosophy, the two opposites divide the circle of the life, with a piece of each in the other.

As data rates required for systems in package (SiPs) increase and their complexity increases, signal integrity issues become increasingly difficult to address. The design flow of the SiP should therefore take into account these issues from the beginning. A design flow aimed at designing the SiP tracks is presented; its suitability for the design of packages comprising multiple stacked memories is verified through a design example. The proposed flow for signal integrity can be integrated easily within the complete design of the SiP.

We analyze the electrical phenomena that can affect the integrity of the communication among different chips within a System in Package (SiP). We address these issues for a real case, for which electrical parameters are extracted from layout and used to build a netlist employed for electrical characterization. We show that crosstalk, and in particular inductive crosstalk, is the electrical phenomenon mainly affecting signal transmission within the SiP. Then,we evaluate the kinds of errors that can be originated. We show that errors caused by inductive coupling among SiP interconnects can be unidirectional only, thus allowing designers to implement error control coding techniques based on All Unidirectional Error Detecting codes. This allows significant cost reduction over the alternate use of non-unidirectional error detecting codes.

This paper presents a survey of the principal architectures and blocks building up a flash memory, describing how these blocks are designed and how their design has changed over the years to satisfy the new specification requests. For example, the continuous supply voltage reduction aimed at portable electronic solutions has forced designers to find innovative design solutions. An overview of the test modes developed for the flash device not only to debug the chip but also to try to improve reliability is given. Ad hoc test modes are useful to deeply increase the analysis capability. Finally, the test methodology for flash memories, a challenge between the test time reduction and better test coverage, is presented.

The ever-increasing demand for portable equipment is leading to the use of flash memory devices for nonvolatile storage. Fast access time and low power consumption are obviously key requirements. Moreover, multilevel storage techniques are mandatory to reduce the cost per megabit. As a consequence, the READ operation becomes more and more critical, and optimized solutions are needed for almost all circuits involved in the read path. This paper examines the whole read path from addresses to data output, and describes several schemes developed to achieve the required high performances.