As an increasingly popular cloud computing model, serverless computing suffers from performance degradation caused by microarchitectural cold start. Previous studies identify the front-end as the bottleneck and explore solutions such as instruction prefetching and restoring Branch Target Buffer. However, they fail to prewarm the Conditional Branch Predictor (CBP), because the large size of its core component, the TAgged GEometric history length predictor (TAGE), makes it impractical to be saved and restored.This paper observes the predictive sparsity of TAGE, where only a small subset of entries can dominate the predictor’s coverage and accuracy. We introduce Khepri, a memory efficient CBP prewarming mechanism that uses a TAGE Crystallization algorithm to identify these dominant entries. Khepri records them in main memory and restores them to prewarm TAGE at the next invocation. Khepri achieves a 1.57× speedup over the baseline and outperforms the state-of-the-art technique by 14%, requiring only 1.54KB in main memory on average.

As deep neural networks grow in size, their computational and energy demands pose significant challenges for efficient hardware acceleration. Quantization reduces storage, data movement, and computation costs by lowering numerical precision. While 8-bit integer (INT8) is widely adopted, lower precisions such as INT6 and INT4 can also maintain acceptable accuracy with specialized quantization techniques, motivating accelerators that support multiple precisions. This paper presents BitPair, a precision-scalable accelerator that employs a 2-bit serial dataflow to perform general matrix multiplications (GEMM). BitPair supports signed and unsigned integer operations at 2/4/6/8-bit precision for both input matrices. Implemented in Verilog and synthesized in TSMC 12nm technology, BitPair is compared with two prior precision-scalable architectures, Loom and BitShare. Evaluation shows that BitPair achieves up to 1.63 × lower bandwidth, 1.19 × smaller area, and 1.14 × lower power compared with Loom and BitShare.

Sparse data structures are ubiquitous in graph analytics, machine learning, and high-performance computing. Algorithms operating on these structures typically exhibit highly irregular data-dependent memory access (DDMA) patterns, leading to frequent cache misses and degraded memory performance. Prior work on hardware prefetching to mitigate DDMA-induced misses falls into two categories: address-based methods that sample correlated sequences of load data and addresses from cache miss streams, and instruction-based methods that record instruction-level dependency chains. Although both learn single relations effectively, they struggle with multi-level range relations prevalent in DDMA-intensive workloads, leaving substantial prefetching opportunities unexploited. In address-based schemes, misses from deeper-level consumers are often miscorrelated with the producer. Moreover, out-of-order execution and the range relations themselves perturb sampling, yielding mismatched load instances. In instruction-based schemes, chain-structured representations and suboptimal learning strategies prevent the construction of complete dependency chains for these relations. To overcome these limitations, we present Thoth, a hardware prefetcher that operates at the granularity of explicit producer-consumer load pairs rather than constructing dependency chains. Thoth detects such pairs via register-level dependency tracking. It adopts an annotation-directed load sampling strategy that annotates matched producer-consumer load instances and samples only those annotated instances, thereby robustly uncovering DDMA patterns—including multi-level range relations—while avoiding mismatches. To maintain annotation correctness across pipeline flushes, Thoth employs precise load annotation, which leverages reorder identifiers to resume or terminate annotation precisely. On a suite of DDMA-intensive benchmarks, Thoth delivers a 51.1% speedup over a no-prefetching baseline and outperforms two state-of-the-art DDMA prefetchers by 14.7% and 8.2%, respectively.

The Network-on-Chip (NoC) has emerged as a vital interconnect fabric in multi-core processors. However, the implementation of virtual networks requires multiple message queues at each router’s input port to prevent protocol-level deadlocks, resulting in substantial area and power overheads. This complexity poses challenges in maintaining performance within a constrained area budget. In this paper, we introduce PCMT, a virtual-network-free mechanism that leverages the inherent priority of directory-based coherence messages to resolve protocol-level deadlocks within the NoC. Experimental results show that PCMT outperforms both baseline and state-of-the-art solutions across systems with varying numbers of virtual networks. In a MOESI-hammer protocol system with 6 virtual networks, PCMT achieves comparable performance while reducing input buffer overhead by up to 63% compared to the baseline. In a MOESI directory system with 3 virtual networks, PCMT improves overall execution time by up to 4.0% with the same input buffer resources. Additionally, PCMT demonstrates superior deadlock resolution speed and bandwidth consumption compared to the state-of-the-art work.

Large language models (LLMs) have achieved great success in areas such as language understanding and text generation. However, their massive parameters incur high computational, storage, and energy costs, making deployment on resource- and power-constrained edge devices particularly challenging. Block Floating Point (BFP) reduces storage and computational overhead by grouping data into blocks and aligning them to the maximum exponent within each block, converting them into low-bit fixed-point numbers. Bidirectional Block Floating Point (BBFP) extends BFP by aligning data within a block to two different exponents, reducing quantization error for small values. However, at ultra-low bit widths, both methods suffer from severe accuracy degradation due to their sensitivity to outliers, which limits their ability to achieve aggressive energy savings. In addition, the exponent alignment procedure in these schemes inherently introduces bit-sliced sparsity, an opportunity that remains largely unexplored for further improving energy efficiency on edge accelerators. To address these challenges, we propose an energy-efficient dual-sparsity LLM accelerator (DSLA) that supports the HiMix-BFP data format. HiMix-BFP improves low-bit accuracy by preserving extra mantissa bits for the maximum value and adaptively selecting BFP or BBFP per block. The DSLA architecture efficiently exploits both value and bit-sliced sparsity across different bit widths to further enhance energy efficiency by employing low-bit computational units, load-balancing mechanisms, and a hierarchical bit-accumulation array. Experimental results demonstrate that HiMix-BFP reduces perplexity by up to 76%, while DSLA achieves up to$1.39\times $higher throughput and$1.59\times $greater energy efficiency compared to SOTA accelerators.

The inference of large language models (LLMs) on edge devices has always been a challenge, the autoregressive inference and enormous number of parameters result in long inference latency. Although speculative decoding is proposed for inference acceleration, it poses challenges for hardware accelerator design, as the differing computational characteristics of the drafting and verification stages make it difficult to optimize both chip area and hardware utilization. This brief introduces fused speculative decoding (FSD) to optimize LLM inference on edge devices by unifying all the operations to general matrix multiplications during inference. The proposed FSD-Infer algorithm fuses the drafting and verification phases of conventional speculative decoding and enables weight sharing, reducing off-chip memory access, and inference latency without requiring retraining or fine-tuning. For hardware, we introduce FSD-Acc, an area- and utilization-efficient hardware accelerator that efficiently executes the fused operations enabled by FSD-Infer. Experimental results show that compared with autoregressive inference, FSD-Infer reduces EMA by up to 26.11%, enhances arithmetic intensity by$10.26\times $, and speeds up GPU inference by up to$1.38\times $. When deployed on Xilinx ZCU102 FPGA board at 200 MHz working frequency, FSD-Acc achieves the best area efficiency and energy efficiency, outperforming the state-of-the-art LLM accelerator for edge inference by$2.53\times $(TPS/kDSP),$5.90\times $(TPS/kLUT) and$2.02\times $, respectively.

Protecting return address integrity (RAI) on high-performance embedded processors (HPEPs) is more challenging than on traditional microcontroller units (MCUs) or server processors. Isolation-based schemes such as shadow stacks fail against hardware memory threats, while crypto-based schemes remain vulnerable to forgery and replay attacks. To address the challenges of RAI protection in HPEPs, this article presentsRAEnc, a novel crypto-based scheme, which provides comprehensive RAI against both forgery and replay attacks with negligible performance overhead via hardware–software co-design. We first introduce the metadata compression during return address encryption (MCRAE), a cryptographic primitive compressing the call stack’s integrity state into a single, register-resident value using custom RISC-V instructions, thereby eliminating the memory attack surface. We then detail the stall-less encryption/decryption unit (EDU) that is tightly coupled with the processor pipeline. By employing speculative scheduling, a low-latency 128-bit QARMA unit, encryption/decryption cache (EDCache), and multichain parallelism, the EDU eliminates pipeline stalls common in decoupled accelerators. Implemented on the open-source BOOM processor,RAEncincurs a negligible 0.2% performance overhead on embedded and SPEC CPU2017 workloads with modest hardware cost, outperforming existing crypto-based RAI schemes in both security and performance.

American Sign Language (ASL) has drawn growing attention due to its extensive application potential. This brief presents an ultralow-power real-time high-accuracy ASL recognition system (LRASL) for smart edge devices. It balances accuracy and power efficiency via a six-stage advanced hand region segmentation engine (AHRSE) and a hardware-sharing hierarchical self-similar binarized neural network engine (HSBNNE). The AHRSE compresses$640\times 480$RGB565 inputs into$32\times 32$binary gestures through six-stage processing, achieving a$4800\times $reduction in size, and boosting HSBNNE accuracy by 1.3%. Notably, similar gestures persist in binarized ASL gestures after extraction, increasing recognition difficulty and elevating hardware’s power consumption/resource demands. To address this, a novel miniaturized hierarchical self-similar binarized neural network (HSBNN) model with shared layers and dual self-similar expert branches is proposed. The HSBNNE, built on the HSBNN model, recognizes ASL gestures (similar and dissimilar ones) from coarse to fine, which achieves 95.8% recognition accuracy with only 3.96 MOPs and 2.86 KB parameters. The self-similar expert branches enable maximal reuse of hardware resources, reducing hardware overhead and lowering power consumption. Implemented in TSMC 28-nm CMOS, the proposed LRASL achieves a power consumption of only$45.2~\mu $W and a latency of 33.3 ms when operating at an 800-kHz clock frequency and 0.6-V supply voltage.

Attention-based LLMs excel in text generation but face redundant computations in autoregressive token generation. While KV cache mitigates this, it introduces increased memory access overhead as sequences grow. We propose Sella, a hardware-software co-design using cluster-based associative arrays to predict Q-K correlations, enabling selective KV cache access and reducing memory access without retraining. Sella includes a specialized accelerator featuring a prediction engine to improve performance and energy efficiency. Experiments show Sella achieves $2.1 \times$, $93.8 \times$, $31.4 \times$, and $53.5 \times$ speedup over SpAtten, Sanger, TITAN RTX GPU, and Xeon CPU, respectively, reducing off-chip memory access by up to $66 \%$ with negligible accuracy loss. -Large Language Models, KV Cache, Accelerator

The linear and nonlinear mismatches in time-interleaved analog-to-digital converter (TIADC) both severely degrade the system’s performance. Calibration techniques play a crucial role in restoring TIADC’s optimal performance. However, existing techniques have application limitations in nonlinear modeling and exhibit one-sidedness in error detection, leading to overfitting. This paper proposes a new background calibration for mixed linear and nonlinear errors. A unified model with wide applicability is presented to characterize mixed error generation based on the Taylor and the Volterra series. Then the errors are calibrated by a high-precision algorithm which addresses the issues of high dimensional optimization and overfitting problems simultaneously. The proposed technique is verified with simulations in MATLAB and experiments in a 16-bit 4-channel 260MS/s board-level prototype, improving the SFDR from 35.5 dB to 73.3 dB with a dual-tone input at 67.6 MHz and 119.6 MHz.

Computing-in-memory (CIM) based on embedded nonvolatile memory (NVM) realizes energy-efficient acceleration of convolution neural network (CNN) with less data movement and high computing parallelism. Because the deployment environments for edge devices are usually subject to changes, it is necessary for the CIM accelerators to support light-weight on-chip training with efficient implementation for environmental adaptation. However, previous CIM accelerators for edge devices mainly realize the inference while the training is performed on cloud. The limited endurance of NVMs hinders the CIM accelerators from supporting on-chip training that involves a large number of weight updates. In this paper, an endurance friendly CIM accelerator based on NVM, EF-CIM, is presented with bit-aware wear-leveling for efficient on-chip training in edge devices. Firstly, the bit split weight mapping (BSWM) splits the multi-bit weights into individual bits and stores them in the array alternately. Then, the bit-aware wear-leveling (BAWL) reduces the NVM updates by using verify write and block switch methods. An EF-CIM accelerator with BSWM and BAWL that is evaluated for 8-bit inputs and weights in the 28nm process achieves ~3.58/3.26 TOPS/W energy efficiency for feed-forward/ back-propagation, 5X lower computing latency. The BAWL also alleviates the wear of NVMs by 40X, achieving high NVM training reliability.

ReRAM has emerged as a promising candidate for computing-in-memory due to its excellent compatibility with advanced CMOS processes, high density, and non-volatility. Meanwhile, Digital Computing-in-Memory (DCIM) offers higher energy efficiency than its analog counterpart and supports full-precision processing. However, existing ReRAM-based DCIMs are hindered by error-prone readout and low input parallelism. The inefficient bit-width reconfiguration also incurs significant hardware overhead during neural network mapping. This paper reports a 64Kb DCIM engine based on 1T2R ReRAM bitcells for multiply-and-Accumulate(MAC) acceleration. The ternary-input Booth-assisted multiply-in-memory (TB-MIM) flow allows bi-state ReRAM with limited readout margin to achieve high-accuracy computation with high parallelism. The corresponding reconfigurable vector adder-tree and accumulator (ReV-A2) effectively facilitate practical hybrid-precision network mapping. Simulations show that the proposed DCIM engine achieves a normalized throughput rate of 284.44 GOPS/Kb and an energy efficiency of 730.16 TOPS/W, surpassing previous ReRAM-based DCIM designs by$3.3\times $.

Under the threat of quantum computers, the public-key cryptosystems need to transition to the Post-Quantum Cryptography (PQC) standards. However, this migration process is hindered by the diverse mathematical structures of PQC standards as well as the side-channel attacks, especially for the resource-constrained and physically accessible edge devices. To address this issue, we present ARV-Q, an adaptive RISC-V vector processor that efficiently offers unified support of PQC standards and side-channel security enhancement. Firstly, we propose an adaptive RISC-V-based computing paradigm to adapt to PQC algorithms across diverse mathematical bases, the core of which is a crypto extension supporting all PQC standards plus schemes in the fourth round in NIST standardization process. This crypto extension can well cooperate with the RISC-V Vector Extension (RVV) and is capable of adaptive operator-type support. Second, we design a highly resource-efficient vector crypto engine featuring versatile Butterfly Units and multi-Selected-Element-Width-adaptive modular arithmetic constructs, achieving high hardware utilization with configurable parameter settings. The crypto engine is integrated into the RISC-V core via an agile extension interface capable of bridging all types of register transfers. Besides, due to the capability of cooperative hybrid vector computing of RVV and crypto extension, ARV-Q can flexibly adapt to side-channel attacks with no hardware overhead while maintaining high performance. ARV-Q is implemented in 22nm process, and post-layout simulations are conducted. Results outperform the state-of-the-art counterparts in primary PQC standards with 1.21-5.14× better latency and more than 4.41× better area efficiency.

As heterogeneous platforms scale, power management issues grow increasingly critical. On-chip power awareness is fundamental to effective power management on such platforms. However, the integration of diverse components leads to higher power consumption and more complex power patterns, complicating the perception of power distribution. To address this challenge, this article presents COordinating BInary Trait (COBIT), which focuses on the design and optimization of on-chip power meters (OPMs) for heterogeneous design, enabling power management in large-scale systems. COBIT extracts essential bitwise wires as features, learns a boosting model based on binary trees, and implements the OPM for runtime power prediction. Additionally, multiobjective optimization algorithms are employed in the design space exploration of the power meter to ensure an accurate and low-overhead integration. Experimental results demonstrate the capabilities of COBIT on heterogeneous hardware. Using only 0.028% bitwise power proxies of all RTL wires in the NVIDIA deep learning accelerator (NVDLA) and 0.036% in the Berkeley out-of-order machine (BOOM) processor core, the per-cycle models achieve a mean absolute percentage error (MAPE) of 1.69% and 2.49%, respectively. Regarding the success rate of predictions on power peaks in NVDLA, COBIT achieves a maximum performance improvement of 12.93% and an average improvement of 8.11% over existing methods. Moreover, the gate-area/power overhead of our OPM on BOOM and NVDLA is 1.25%/0.217% and 0.49%/0.097%, respectively, while performing per-cycle power prediction in just three cycles. Unlike previous approaches, which struggle with balancing accuracy and efficiency, COBIT effectively addresses both challenges, delivering unprecedented benefits for large-scale systems.

Computing-in-memory (CIM) is a promising technique for hardware acceleration of neural networks (NNs) with high performance and efficiency. However, conventional dense mapping scheme cannot well support the compression and optimization of irregular sparse NNs. In this paper, we propose a heuristic and greedy weight remapping scheme for irregular sparse neural networks implemented on CIM accelerator in edge AI applications. The genetic algorithm (GA) is proposed for the first time to be utilized in the column shuffle for sparse weight remapping. Combined with the granularity exploration of the CIM, the proportion of the compressible all-zero rows increase remarkably. A greedy algorithm is then employed to planarize the unevenly compressed units, thus to improve the storage utilization of the crossbar. For hardware optimization, the pipeline is customized with a zero-skipping circuit to leverage the bit-level activation sparsity at runtime. Our results show that the proposed remapping scheme achieves 70%-94% utilization rate of the sparsity, and an average of $1.3 \times$ increment compared with the naive compression. The cooptimized CIM achieves $3-7.6 \times$ speedup and $2.1- 4.8 \times$ energy efficiency, compared with the baseline for dense NNs.

The National Institute of Standards and Technology (NIST) has selected FALCON as one of the standardized digital signature algorithms against quantum attacks in 2022. Compared with the other post-quantum cryptography (PQC) schemes, lattice-based FALCON is more appropriate for future Internet of Things (loT) applications due to the fastest signature verification process and the lowest transmission overhead. In this paper, we propose a custom extension based on the RISC-V scalar-vector framework for efficient implementation of FALCON. To our best knowledge, this work is the first hardware-software co-design for complete FALCON signature generation and verification routines. Besides, we design the first FALCON Gaussian sampling hardware and a RISC-V vector extension (RVV) based domain-specific core. The proposed architecture accelerates kernel operations in FALCON, such as discrete Gaussian sampling, number theoretic transform (NTT), inverse NTT, and polynomial operations. Compared with the reference implementation, results on the gem5-RTL simulation platform present a speedup for signature generation and verification of up to 18 x and 6.9 x.

To accommodate the requirements of increasingly diverse applications, the scale of System-on-Chip (SoC) has extended beyond single-chip, evolving towards chiplets. This expansion is accompanied by a significant increase in the number of functional IPs. Each new IP undergoes a lengthy development process to meet expected performance and ensure compatibility with existing SoCs. The conventional development process is generally divided into several distinct stages, including architecture exploration, RTL development, standalone testing, and integration verification. As IP complexity escalates and coupling with the software stack becomes intricate, the standalone testing phase fails to guarantee complete IP functionality. This deficiency leads to extended development periods and necessitates numerous iterative design revisions during the integration verification phase, hindering the efficiency of IP integration into SoC. In this paper, we introduce Chimera, the first co-simulation framework that combines ESL simulators and the FPGA platform. The framework streamlines the conventional development process, providing a direct approach to architecture exploration and integration verification of a Register-Transfer Level (RTL) IP within an SoC running on the gem 5 simulator. We propose three optimizations including an optimistic synchronization mechanism, batch processing, and dataflow merging to enhance the efficiency of Chimera. Our experimental results demonstrate that Chimera can sustain co-simulation speeds comparable to the speed of the standalone gem5 simulator within typical system configurations. Furthermore, Chimera outperforms the state-of-the-art co-simulation framework, achieving up to a $20 \times$ performance improvement.

With the increasing complexity of applications and the improvement of computational power, modern neural networks (DNNs) have become more memory-intensive. To address the bandwidth problem, modern hardware architectures often incorporate multi-level memory to efficiently reuse data with different reuse distances. Additionally, a promising technique to reduce DNN bandwidth requirements is layer fusion which reuses inter-layer data at on-chip memory. However, previous studies on inter-layer data reuse scheduling have focused primarily on reusing at the outermost on-chip memory, neglecting the exploration of multi-level architecture, which represents a significant optimization space.

Concurrent access to shared data has always been a challenge for developing multi-threaded programs and a bottleneck in the performance of Chip-Multiprocessor (CMP) systems. The challenge has been exacerbated by the need to augment processor cores and network bandwidth to fulfill the low-latency demands of ever-expanding data processing. Existing commercial best-effort Hardware Transactional Memory (HTM) is a common and effective solution. However, its architectural constraints prevent transactions from surviving in exceptions, cache overflow, and coexisting with a non-speculation fallback path, leading to unstable performance and diminishing favor. In this paper, we propose three lightweight mechanisms designed to mitigate the limitations of the best-effort HTM architecture to enhance performance stability. One is the recovery mechanism that supports the dynamic revocation of toxic conflicting requests, dramatically reducing the potential of livelocks. The second is the HTMLock mechanism with hardware and software co-design, which allows transactions using HTM and locks to run concurrently except when encountering actual conflict. Lastly, the switchingMode mechanism enables a running transaction to proactively attempt to switch to HTMLock mode in the event of a non-conflict-induced abort. Gem5 infrastructure is extended to validate and evaluate our mechanisms in a 32-core tiled CMP system. Experimental studies show that LockillerTM outperforms the coarse-grained locking scheme under STAMP benchmarks except for the yada workload, irrespective of thread number and cache size. Furthermore, our approach achieves an average of 1.86x and 1.57x speedup in all benchmarks and different threads under a typical cache size and a maximum of 7.79x and 6.73x speedup in high-contention benchmarks under extreme scenarios with only 8KB L1 cache and 32 threads, compared to best-effort HTM and state-of-the-art HTM respectively.

The beamforming technique has been widely used to improve the link budget in wireless communications. Compared with the digital beamformer, the analog beamformer has much lower hardware complexity and is more suitable for low-cost mobile applications. In this paper, we consider element-level phase and gain control of the analog beamformer using two phase shifters only. By setting the phase shifts properly, simultaneous 360◦phase and 6-dB gain control (SPGC) can be achieved to form the beam pattern. We first propose a low-complexity SPGC method tailored for massive multiple-input multiple-output (MIMO). Based on the conventional and proposed SPGC methods, we then design the full-featured accelerator (FFA) and the hardware-efficient accelerator (HEA) to accelerate the computing process. These two accelerators are implemented in 28 nm technology. FFA integrates 137 kilogate equivalents (kGE) in a core area of 0.0693 mm2and dissipates 104.4 mw at 2.0 GHz with 16 degrees of parallelism, while HEA can reduce the core area by 44.6% and power consumption by 42.7% without significant performance loss.

In recent years, natural, flexible, and contactless vision-based gesture recognition has received significant attention in human-computer interaction. However, employing convolutional neural networks (CNNs) for RGB or RGB-D gestures can result in excessive power consumption and poor energy efficiency, making them unsuitable for embedded systems. In this paper, we propose a lightweight sparse binarized neural network (sBNN) model for edge gesture recognition that achieves an accuracy of 89.43%-99.92% on four open-source gesture datasets with$\leq 20.26$million operations (MOP) and$\leq 15.83$-Kilobytes (KB) parameters. We find high channel-level sparsity in the activation maps of sBNN when edge gestures are used as inputs. The sparse activation maps have multiple identical activation vectors called sparse activation vectors (SAV), which lead to highly repeated calculations. In order to avoid this issue, we propose a two-stage value prediction approach to skip these calculations, achieving a speedup of 1.03x-1.83x. Moreover, to reduce on- chip memory, the compression technique is applied to the sparse activation maps, providing a compression rate of 1.72x-3.45x. Finally, we implement an energy-efficient sparse BNN accelerator (SBA) on an embedded field-programmable gate array (FPGA). The experimental results show that our SBA has a latency of 26.3-46.8-$\mu \text{s}$, a power consumption of 0.807 W, and an energy efficiency of 536.22-952.70-GOPS/W at 50-MHz frequency. Our SBA offers lower latency, lower power consumption, and higher energy efficiency than previous state-of-the-art gesture recognition accelerators.

Low-level vision algorithms play an increasingly crucial role in a wide range of applications, such as biomedical, security, and autopilot. The low-level vision accelerators have also been extensively researched. As low-level vision is often deployed in embedded devices, its accelerators need to achieve high energy efficiency. Meanwhile, the broad application scenarios of low-level vision contribute to its rapid iteration. Designing energy-efficient accelerators for quickly evolving low-level vision algorithms demands substantial effort. Therefore, a design framework specifically tailored for the generation of low-level vision accelerators is urgently needed. In this article, we propose an end-to-end algorithm-hardware generation framework, EffiVision, on field-programmable gate array (FPGA), aimed at generating highly energy-efficient dedicated accelerators for low-level vision neural networks. EffiVision proposes a hardware template that features multiple parallelisms and large architecture exploration spaces specifically designed to accommodate the characteristics of low-level vision networks. Then, it employs activation-weight aware mixed-precision quantization and FPGA-aware NNLUTs to search the suitable hardware parameters within the hardware template, generating highly energy-efficient accelerators tailored for low-level vision networks. We used EffiVision to perform hardware generation for three low-level vision neural networks fast super-resolution convolutional neural network (FSRCNN), denoising convolutional neural network (DnCNN), and demosaicing convolutional neural network (DMCNN) on Xilinx FPGA development boards, achieving the best energy efficiencies of 174.9, 97.8, and 92.7 GOPS/W, respectively. The generated accelerators of FSRCNN and DnCNN are$1.11\times $and$3.37\times $more efficient than previous works.

We present a cryptography extension built on RISC-V Vector Extension for efficient application of lattice-based post-quantum cryptography, offering custom instructions that can perform vectorized operations on polynomials of variable length and data width. We use micro-operation architecture to simplify the execution of variable-latency vector instructions and propose fracturable modular arithmetic units to support operations on variable coefficient width. On this basis, a vector unit is designed, achieving significant speed-up compared to the state-of-the-art counterparts for number-theoretic-transform-based polynomial multiplication. This cryptography extension is further integrated into the gem5 simulator to evaluate CRYSTALS-Kyber and CRYSTALS-Dilithium; results outperform the state-of-the-art implementations with more than 2.3 × improvement in cycle count.

Speculative execution attacks such as Spectre and Meltdown exploit the wrong execution patch to leak private data. In current state-of-the-art defense strategies, executions of all memory accesses that use speculatively-loaded addresses are blocked, resulting in high overhead. Our key observation is that these blocked memory accesses can be executed without operand-dependent hardware resource usage through value prediction. Therefore, we propose a novel hardware defense framework, named Speculative Value Prediction (SVP), to safely and efficiently execute the potentially unsafe memory accesses earlier. We build SVP on the cycle-accurate Gem5 simulator and its performance improvement is positively correlated with the coverage of value predictors. Experiments show that when using the value predictor with 30%/60%/100% coverage, SVP outperforms the state-of-the-art defense mechanism STT in the Spectre model by 21.5%/50.3%/107.7% respectively, and in the Futuristic model by 28.7%/55.4%/105.7% respectively.

Radiation Hardened by Design (RHBD) is one of the main measures for solving the soft error issue in digital circuits. However, a multi-objective optimization (MOO) problem obviously appears when utilizing the hardened counterparts to replace the original unreliable cells. This paper proposes a MOO framework based on Bayesian Optimization (BO) for balancing design metrics like area, Longest Path Delay (LPD)/power, and Soft Error Rate (SER) while hardening digital circuits, including combinational and sequential circuits. This framework comprises two phases: 1) data preprocessing and 2) multi-objective Bayesian optimization. The first phase makes this framework much more applicable for large-scale circuits through data dimensionality reduction. The second phase is characterized by utilizing a black-box approach to greatly promote the efficiency and accuracy of MOO. Experimental results on benchmark circuits demonstrate that the framework achieves a 1.34x improvement in accuracy, an 11.47x enhancement in efficiency, and a 0.77x reduction in SER, while exhibiting a 4.27x and 0.72x increase in area for combinational and sequential benchmark circuits, respectively, along with a 0.54x increase in LPD and a 1.25x increase in power for Triple Modular Redundancy (TMR) techniques.

With the scaling down of process, single event upset has been a critical issue for integrated circuits. It is much more likely to occur multiple-node upsets (MNUs) in CMOS ICs in advanced technology. However, the problem remains unsolved because of the lack of efficient methods. In this article, a non-redundant triple-node-upset(TNU)-tolerant latch with high reliability is proposed in 28 nm CMOS technology. The proposed latch named KOBE reduces the number of inner-sensitive nodes as well as the redundancy of the TNU-tolerant latch. In simulations, the proposed KOBE latch performs faster and lower power with higher reliability than most of the TNU-tolerant latches proposed before. The post-layout parasitic extracted simulations show that the proposed KOBE latch has an average improvement of 52.5% in a Power-Area-Delay Product (PADP) compared with the recently reported TNU-hardened latch at a supply voltage of 0.9 V, a working temperature of 27 °C. What’s more, by changing the working voltage and temperature, it is proved that the proposed KOBE latch has a better performance in a harsh environment. The results show that the proposed KOBE latch is of high beneficial efficiency and high reliability, thus can be used in safety-critical applications.

A self-biased voltage/current reference (VCR) generator provides bias for its embedded operational amplifier simply by itself. But during the power-up process, it is prone to be trapped into an undesired operating point called Trojan state (TS-UOP) that a conventional startup circuit (CSC) is unable to handle. This paper firstly simulates the power-up process of a self-biased VCR generator and discovers the dominant node that plays the leading role in the power-up convergence. Then, a dominant-node theory is proposed to find the dominant node based on the voltage-vertex directed dependency graph (DDG) and the Weight-Flow algorithm. In order to rescue the dominant node, a Monitoring-Rescue method is proposed as a general approach to enhanced startup circuits (ESCs) to eliminate TS-UOPs. An example of ESCs is designed in a 28-nm CMOS process. The measurement results verify that the ESC successfully helps the self-biased VCR generator converge to the desired operating point (DOP) regardless of the power-up ramping time range of$\mathrm {100~ \mu \text { s} }$to$\mathrm {100~ \text {m} \text { s} }$and the temperature range of$\mathrm {-45~ ^{\circ}C}$to$\mathrm {115~ ^{\circ}C}$.

This paper presents a triple-output piezoelectric energy harvesting (PEH) system with parallel synchronized switch harvesting on capacitors (P-SSHC) rectifier based on shared capacitors. By analyzing the principle of the P-SSHC rectifier, this paper supports the rationality of using shared capacitors to construct the multi-voltage conversion ratio (VCR) switch capacitor (SC) DC-DC converters. In addition, the adoption of a parallel structure in the multi-output SC DC-DC converters reduces the cross-regulation. Simulation results show that the proposed system not only has good input power adaptability (1/3X,1X,2X) but can also provide triple voltage (0.5V, 1V, 2V) with less cross-regulation. The maximum output power is 14.4μW when peak-to-peak open circuit voltage is 1.7V.

This paper presents the first synthesis friendly dynamic amplifier (DA). The proposed fuzzy logic calibration makes its gain robust against process-voltage-temperature (PVT). In addition, the piecewise-linear linearization technique is also proposed for the fuzzy logic to tune the amplification phase, which compensates the time-domain non-linearity of the regeneration voltages, and accelerates the calibration convergence. The proposed DA is designed in 28-nm CMOS process, and verified by post-simulation results. It has a 16 × gain with -3.0%~3.6% deviations at TT corner once the calibration converges within 50 cycles.

A self-biased voltage/current reference (VCR) generator is simple, but suffers from some Trojan states surviving the conventional start-up process. After demonstrating this problem by simulation, this paper reveals the mechanism by identifying and analyzing all of the feedback loops that give rise to multiple Trojan states. Based on the theory, an enhanced start-up circuit is proposed that is capable of removing all Trojan states. Finally, the enhanced start-up circuit is embedded into a self-biased voltage reference generator, and designed in 28 nm CMOS process. The simulation results prove that the enhanced start-up circuit successfully eliminates all Trojan states in a wide temperature range for different process corners.

The 5G edge computing infrastructure should be empowered with quantum attack resistance by implementing post-quantum cryptography (PQC). Among various PQC schemes, lattice-based cryptography (LBC) based on learning with error (LWE) has attracted much attention because of its performance efficiency and security guarantee. In LWE-based LBCs, the Module-LWE-based schemes gain advantage over the others benefiting from the unique polynomial matrix and vector structure. To provide a high-performance implementation of Module-LWE applications for the edge computing paradigm, we propose a domain-specific processor based on a matrix extension of RISC-V architecture. This custom extension encapsulates the matrix-based ring operations with a high-level functional abstraction. A 2-D systolic array with configurable functionality is proposed to perform matrix-based number theoretic transform (NTT) and other arithmetic operations, achieving high data-level parallelism with support for the variable-sized polynomial matrix and vector structure. As this structure of Module-LWE involves no data dependency between different inner elements, an out-of-order mechanism is further developed to exploit the instruction-level parallelism. We implement the proposed architecture under TSMC 28nm technology. The evaluation results show that our implementation can achieve up to$3.5\times $and$3.3\times $improvement in cycle count respectively in Kyber and Dilithium, compared to the state-of-the-art crypto-processor counterparts.

The vigorous development of high compute-intensive applications has led to the demand for maximizing the concurrency of multicore processors. The best-effort hardware transactional memory(HTM) is an important technology adopted by vendors to improve the potential concurrency of multicore processors, but the HTM implementations on commercial products have some drawbacks for its simplicity and need some further optimizations to enable more exploitation of concurrency. In this article, we propose and evaluate a novel design of HTM, called LosaTM, which can provide a scenario-awareness conflict management strategy. By leveraging the proposed feature of multiple-grained coherency maintenance in the coherence protocol, LosaTM resolves most false conflicts at a half-cache-line granularity. Furthermore, we design a winner/aborter vector conflict management algorithm to improve the efficiency of LosaTM in handling friendly-fire and unfairness competition that we have newly defined. In order to coordinate these integrated conflict management strategies, a scheduling strategy is also proposed to adaptively select the appropriate management according to the specific conflict scenario. We use gem5 to simulate LosaTM in detail on an 8-core tiled CMP system, and the simulation result shows that it only causes 0.7% of the L1 cache size hardware overhead while achieving a 38% average execution time reduction on the native STAMP. The speedup also demonstrates that LosaTM outperforms the state-of-the-art designs in previous works.

Single Event Upset (SEU) is one of the most susceptible reliability issues for CMOS circuits in a harsh environment, such as space or even a sea-level environment. Especially in the advanced nanoscale node, the phenomenon of Multi-node-upset (MNU) becomes more prominent. Although a lot of work has been proposed to solve this problem, most of them ignored the need for low power consumption. Particularly, most existing solutions are not effective anymore when operating in low supply voltage. Therefore, this paper proposes a novel Flip-Flop called TRIGON based on a single-phase-clocking structure to achieve low power consumption while being able to tolerate Double-node-upset (DNU), even when operating at lower supply voltages. The experimental results show that TRIGON has a significant reduction in the area and Power-delay-area-product (PDAP). Particularly, it achieves about 80% energy saving on average when the input is static compared with the state-of-the-art circuits.

Homomorphic Encryption (HE) allows untrusted parties to process encrypted data without revealing its content. People could encrypt the data locally and send it to the cloud to conduct neural network training or inferencing, which achieves data privacy in AI. However, the combined AI and HE computation could be extremely slow. To deal with it, we propose a multi-level parallel hardware accelerator for homomorphic computations in machine learning. The vectorized Number Theoretic Transform (NTT) unit is designed to form the low-level parallelism, and we apply a Residue Number System (RNS) to form the mid-level parallelism in one polynomial. Finally, a fully pipelined and parallel accelerator for two ciphertext operands is proposed to form the high-level parallelism. To address the core computation (matrix-vector multiplication) in neural networks, our work is designed to support Multiply-Accumulate (MAC) operations natively between ciphertexts. We have analyzed our design on FPGA ZCU102, and experimental results show that it outperforms previous works and achieves over an order of magnitude acceleration than software implementations.

Conventional hardened cells are not robust enough to single event upset (SEU) in 28nm technology due to the scaling of the transistors. High soft error rate is caused by particle striking at cells and logic circuit in SRAM. This work proposes an SEU robust dual access 12T (DA-12T) SRAM with a radiation hardened crossbar-based peripheral circuit (CBPC). The proposed cell with 209% area penalty is more SEU robust than most cells. The CBPC can reduce the read failure rate of SRAMs. The new sense amplifier ensures the correct and rapid reading operation speed when suffering read disturbance. The experiment results show that the SEU cross-section of proposed cell is 60% of standard cell with dummy. Almost no read failure is observed in SRAM with CPBC when operational frequency exceeds 40MHz. Further investigation indicated that DA-12T cell and well isolation technique can reduce the read failure rate.

With the continuous scaling-down of transistors, the soft error issue of the combinational circuit becomes more serious. Triple Modular Redundancy (TMR) and Gate-Sizing (GS) are commonly used hardening methods for combinational circuits. However, the traditional TMR method is often applied at the module level, causing a large area overhead. Therefore, to explore the feasibility of refined and more general TMR, a General Efficient TMR (GE-TMR) method is proposed in this paper. Furthermore, since the hardening process is a multi-objective optimization problem, a Solution Distribution Optimized NSGA-II (SDON) algorithm is proposed. It features a trade-off between Soft Error Rate (SER), delay, and area. Based on the SDON, we systematically characterized and compared the three hardening methods, which are GE-TMR, GS, and MIX (a hybrid application of GE-TMR and GS). The experimental results show that GE-TMR can provide lower SER solutions (SER reduction >88%) than GS (SER reduction >85%) when the area overhead >200%. By combining GE-TMR and GS, in the interval of 100%81%) than the two hardening methods optimized separately (SER reduction of 64% and 80% for GE-TMR and GS, respectively).

With the growing applications of Graph Convolutional Networks (GCN), there is also an increasing demand for its efficient hardware acceleration. Compared with CNN tasks, GCN tasks have new challenges such as randomness, sparsity, and nonuniformity, which will lead to poor performance of previous AI accelerators. In this paper, we propose DyGA, a hardware-efficient GCN accelerator, which is featured by strategies of graph partitioning, customized storage policy, traffic-aware dynamic scheduling, and out-of-order execution. Synthesized and evaluated under TSMC 28-nm, the accelerator achieves an average throughput of over 95% of its peak performance with full utilization of hardware on representative graph data sets. Having a high area-efficiency with 0.217 GOPS/K-logic-gates and 8.06 GOPS/KB-PE-buffer, and thus an energy-efficiency of 384GOPS/W, the proposed accelerator outperforms previous state-of-the-art works in the sparse data processing.

Soft error is a major reliability concern in advanced technology nodes. Although mitigating Soft Error Rate (SER) will inevitably sacrifice area and power, few studies paid attention to optimization methods to explore trade-offs between area, power and SER. This paper proposes an optimization framework based on Bayesian approach for soft-error-tolerant circuit design. It comprises two steps:1) data preprocessing and 2) Bayesian optimization. In the preprocessing step, a strategy incorporating k-means algorithm and a novel sequencing algorithm is used to cluster Flip-Flops (FFs) with similar SER in order to reduce the dimensionality for the subsequent step. Bayesian Neural Network (BNN) is the applied surrogate model for acquiring the posterior distribution of three design metrics, while the Lower confidence bound (LCB) functions are employed as acquisition functions to select the next point based on BNN when optimizing. Finally, the non-dominated sorting genetic algorithm (NSGA-II) is used to search the Pareto Optimal Front (POF) solutions of three LCB functions. Experimental results demonstrate the proposed framework has a 1.4x improvement in accuracy and a 70% reduction in SER with acceptable increases in power and area.

This paper presents a methodology of the clock polarity inversion (CPI) technique to design integer and halfinteger frequency dividers. Based on a generalized structure of CPI dividers, the CPI-state allocation algorithms are derived for a CPI divider to achieve desired division ratio and duty cycle. The methodology is then demonstrated by a programmable CPI divider that is designed in a 65-nm CMOS process and verified by measurements.

This paper presents a synthesis friendly digital-like delta sigma (ΔΣ) analog-to-digital converter (ADC) based on voltage-controlled oscillator (VCO). The VCO is improved for low power and easiness of calibration. The proposed calibration technique establishes an extra feedback loop to prevent the center frequency of VCO from process variation. Taking the digital-like analog/mixed-signal (AMS) design flow, a 750MS/s ΔΣ ADC is designed in both 28nm and 65nm CMOS technologies with process variation tolerance and process migration verified by post-layout simulation. It is fabricated in 65nm CMOS technology and verified by measurement.

Conventional radiation-hardened cells of static random access memory (SRAM) are not robust enough in 28 nm technology, due to partial immunity of single-event upset (SEU) effect (Quatro-based cells) or insufficient critical charges in sensitive nodes (conventional stacked cells). The reduction of read noise margin (RNM) at the low supply voltage (VDD) confines these cells from low VDD applications. We propose a novel interleaving stacked-14T (ILS-14T) cell which prevents voltage transient from propagating to other redundancies. The ILS-14T cell can be resilient to both 0-1 and 1-0 upsets by injecting 12 mA in sensitive nodes. The critical charges of the ILS-14T cell are substantially larger than most other hardened cells at VDD from 0.3 to 0.9 V. The RNM of the ILS-14T cell is two times of most Quatro-based cells at 0.3 V VDD and larger than most cells at 0.6 and 0.9 V VDD. The area of occupation is 334% of the conventional 6T cell, which equals other 14T cells. The static-dynamic decoder array with 20%-40% area penalty and 116%-132% delay of rising edge, when compared with the conventional one, reduces the read failure rate by preventing single event transients (SETs) from propagating to unexpected word lines (WLs).

Aimed at improving the resistance against power analysis attacks, a systematic and architectural design approach for multicore processors is proposed in this article and is demonstrated in an eight-core prototype platform with low performance overhead and hardware cost. In order to introduce randomness in both the time dimension and the amplitude dimension and make realignment extremely difficult, the proposed multicore platform leverages several methods together, such as random task scheduling (RTS), random insertion of operations (RIO), and frequency and phase randomization (FPR). Moreover, a power state monitoring and control (PSMC) scheme is proposed to defend against power analysis attacks by keeping enough background noises. A test chip of the proposed multicore processor is fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS LP technology and can operate at up to 800 MHz with a 1.2-V supply. The Advanced Encryption Standard (AES) algorithm with these randomization methods is implemented on the processor. Measurement results show that the correlation power analysis (CPA) attacks and the power analysis attacks based on convolutional neural networks (CNNs) are unsuccessful even with 2 000 000 power traces when all the countermeasures are used.

This letter proposes a novel 1.5-D algorithm for multi-channel electroencephalogram (EEG) compression. The proposed algorithm only needs to perform 1-D Discrete Wavelet Transform (DWT) rather than the 2-D version employed by previous works, and thus it results in lower computational complexity and power dissipation. In this algorithm, a new 2-D arranging method that exploits correlations between different sub-bands is developed to concentrate the energy, which causes more efficient compression using No List Set Partitioning in Hierarchical Trees (NLSPIHT) algorithm. Experimental results demonstrate that the proposed algorithm outperforms 2-D NLSPIHT algorithm under the same compression ratio (CR) and it is slightly inferior to 2-D SPIHT algorithm in the near-lossless compression regime, but it can provide a better fidelity with respect to higher CRs.

Pairings are attractive and competitive cryptographic primitives for establishing various novel and powerful information security schemes. This paper presents a flexible and high-performance processor for cryptographic pairings over pairing-friendly curves at high security levels. In this design, hardware for Fp2arithmetic is optimized to accelerate the pairing computation, and especially a combined modular multiplier, which implements (AB + CD) based on Montgomery method, is proposed. This combined multiplier has the data path delay close to that of a single multiplier implementing (AB) but saves 20% area cost compared with two single multipliers. The Design I of the proposed processor is the first fabricated chip for pairing cryptography. An improved version, Design II, is implemented using TSMC 65-nm CMOS technology and achieves the working frequency of 633 MHz after placing and routing. As demonstrated, the optimal ate pairings of 126- and 128-bit security can be computed by Design II in 0.521 and 0.554 ms, respectively. These results outperform the hardware implementations reported by previous works.

This brief proposes an ultralow-voltage four-read-port and two-write-port multiported register file with a novel architecture of read word-line sharing strategy for energy/area efficiency. Static read circuits and memory cells with nonminimum channel length are introduced to improve the ultralow-voltage performance. The chip of this register file is fabricated in 65-nm LP CMOS process and occupies the area of 0.019 mm$^{2}$ . Test results show that the minimum operation voltage is 320 mV with its corresponding max frequency 110 KHz. The minimum energy consumption is 0.94 pJ/cycle at the point of 400 mV, 850 KHz, corresponding to 0.15 fJ/port/bit/cycle after normalization. Compared with the state-of-the-art designs, it improves energy efficiency by 25% and saves the area by 58.7%.

The modular multiplication (MM) is a key operation in cryptographic algorithms, such as RSA and elliptic-curve cryptography. Multicore processor is a suitable platform to implement MM because of its flexibility, high performance, and energy-efficiency. In this paper, we propose a block-level parallel algorithm for MM with quotient pipelining and optimally map it on a network-on-chip-based multicore platform equipped with broadcasting mechanism. Aiming at highest performance, a theoretical speedup model for parallel MM is also developed for parameter exploration that optimizes task partitioning. Experimental results based on a multicore prototype show that compared with the sequential MM on single core, the parallel implementation proposed in this paper maximizes the speedup ratio with regard to given intercore communication latency.

The attacks such as Denial of Service (DoS) violate the security of Network-on-Chip (NoC) which emerges as a promising solution for multi-core system. In this paper, we explore the robustness of mesh-based NoC architecture under various flooding-based DoS attacks. Simulation results reveal that the robustness of NoC architecture can be correlated with parameters such as routing algorithm, the number and positions of attacked nodes. It indicates that deterministic routing algorithm xy will result in less performance degradation than using other four adaptive routing algorithms studied in this paper when the attack traffic rate is lower than 0.65. However, the opposite conclusion can be made if much higher attack traffic rate is used. The performance degradation would escalate with the increasing number of at-tacked nodes. Moreover, the locations of attacked nodes will have an impact on the degree of performance degradation. Last but not least, some design guidelines for NoC against DoS attacks are proposed.

Low-power design has become a key technology for battery-power biomedical devices in Wireless Body Area Network. In order to meet the requirement of low-power dissipation for electrocardiogram related applications, a down-sampling QRS complex detection algorithm is proposed. Based on Wavelet Transform (WT), this letter characterizes the energy distribution of QRS complex corresponding to the frequency band of WT. Then this letter details for the first time the process of down-sampled filter design, and presents the time and frequency response of the filter. The algorithm is evaluated in fixed point on MIT-BIH and QT database. Compared with other existing results, our work reduces the power dissipation by 23%, 61%, and 72% for 1 ×, 2 ×, and 3 × down-sampling rate, respectively, while maintaining almost constant detection performance.

Montgomery multiplication is the kernel operation in public key ciphers. Aiming at parallel implementation of Montgomery multiplication, this brief presents an improved task partitioning of the Montgomery multiplication algorithm for the multicore platform with area-efficient processors. Several multicore platforms are designed to verify the efficiency of parallelization. The fastest platform takes 3460 cycles to finish a 1024-b Montgomery multiplication, which is six times faster than a single MIPS processor and three times faster than the pSHS parallelization based on a platform with eight MicroBlaze cores.

A multi-task-oriented security processing architecture is presented in this paper. This architecture contains a host microprocessor and multiple security processors (SP). The SP could integrate dedicated Crypto-Engines, which provides functional extensibility. And the performance scalability and multi-task parallelism could be enhanced by increasing the number of SPs on system bus. It's demonstrated that this architecture greatly improves the system efficiency. A test chip is implemented based on SMIC 0.18 um standard CMOS technology, and its functionality is well verified.

A low-cost cryptographic processor for security embedded system is presented in this paper. The processor, without any assistance of dedicated cryptographic coprocessors, is scalable and very efficient for popular cryptographic algorithms such as RSA/ECC, AES, Hash, etc. Based on SMIC 0.18 um standard CMOS technology, the core circuit of the test chip has only about 32 k gates, and a max frequency of 200 MHz, under which the 1024-bit RSA algorithm takes only 150 ms and the throughout of AES reaches 256 Mbits/s.

A full-custom design of AES SubByte module based on sense amplifier based logic is proposed in this paper. Power consumption of this design is independent of both value and sequence of data. Therefore this design is resistant to power analysis attack. This design is implemented using SMIC 0.18 um CMOS technology. Simulation results show that it can work at the frequency of 83.3 MHz, and its total area is about 0.85 mm2. This design is suitable for application in the hardware implementation of symmetric-key cryptographic devices that have high security demand.

In this paper, we present an optimal frame synchronization scheme for DVB-S2 system. The scheme is based on differential detection and non-threshold peak search algorithm to achieve frame synchronization. By further analyzing the structure of the Physical Layer Header (PLHEADER) that consists of Start of Frame (SOF) and Physical Layer Signalling Code (PLSC), we find some useful properties that can enhance the frame synchronization and reduce the complexity of its implementation. We also introduce some optimizations into the algorithm. Especially, the modifications made on the peak search algorithm improve the overall performance of the frame synchronization. The experimental results show that the optimal frame synchronization can be achieved under large carrier frequency offset (as large as 5MHz at 25MSps) and low SNR threshold of −2.3dB. Compared with previously proposed approaches, the scheme described in this paper takes less time to acquire frame synchronization and seems to be more robust.

In impulse-radio ultra-wide band (IR-UWB) communications, even a small timing error would lead to a serious degradation in system performance in the multi-path circumstance. To deal with the challenge, a novel hybrid synchronous sampling timing locked loop is proposed in this paper. Timing error detector, the crucial unit of TLL, is realized based on a maximum-likelihood estimation method. Both mathematical analysis and simulations on S-Curve and timing error variance indicate a high performance of the proposed TLL at low signal to noise rate. It is also demonstrated that in the environment of IEEE 802.15.3a Multi-path channels, the proposed TLL improves system bit error rate (BER) performance by two orders of magnitude when the timing jitters are around half a pulse duration. Furthermore, it is observed through simulations that five figures selective Rake receiver is advisable for a satisfactory system BER performance.

A SoC design for applications of OMA DRM 2 Agent in mobile phones is presented in this paper, which has been verified by Altera Stratix EP1S80B956C6 FPGA development board. Several design aspects, which include an embedded 32-bits RISC CPU and AMBA™ bus system, a DRM Agent accelerator, a high-performance TRNG, several interfaces and reasonable hardware/software partition, making it very efficient for the OMA DRM 2 application. Based on SMIC 0.25μm standard CMOS technology, the proposed SoC platform can work under the frequency of about 76MHz, and the core circuit is 112k gates, making it suitable for low-cost design. Besides, memory protection unit is added to enhance the security. Therefore, the proposed SoC platform has a fine potential in application.

In this paper, a novel synchronization method for IR-UWB systems is proposed. Integrate-and-dump operations at the symbol rate are done over the product of the received signal and its Ts-delayed replica. The relative proportion of the two parts constituting these symbol-rate samples, termed the "energy-proportion" in this paper, makes it possible to achieve frame-level synchronization in a fast and reliable way. Two propositions were developed to estimate the energy-proportion in both nondata-aided (NDA) and data-aided (DA) modes, and a training pattern was designed for the DA mode. Simulations indicate that the DA proposition outperforms NDA in terms of both mean square error and bit-error rate. This new synchronization method eliminates the slide-correlating operation required in most existing alternatives, and thus considerably shortens the synchronization time and reduces the complexity.

A platform-based SoC named as Firebird is presented in this paper, which is used for the applications of information security. Several design aspects, which includes the embedded 32-bit RISC CPU and AMBA controller, the reconfigurable and scalable public-key crypto-coprocessor, high-performance TRNG and several low-power schemes, make Firebird very efficient for the client-end applications of information security. Also the test results of this prototype chip indicate that Firebird can work with all these features efficiently, and has some obvious advantages over other designs in the literatures.