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Sheng-Chiech Liang

dblp:02/4136 · DBLP profile ↗
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3ranked-venue papers
0as first author
0since 2021 · last 1992
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware reliability and fault tolerance · 33% Integrated circuit design · 33% Electronic design automation · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance › error detection and correction
concurrent error detection and correction
0.011992
Concurrent Error Detection and Correction in Real-Time Systolic Sorting Arrays · IEEE Trans. Computers 1992
Electronic design automation › hardware verification and test › concurrent checking
self-checking checker design
0.011992
Concurrent Error Detection and Correction in Real-Time Systolic Sorting Arrays · IEEE Trans. Computers 1992
Integrated circuit design
VLSI design
0.011992
Concurrent Error Detection and Correction in Real-Time Systolic Sorting Arrays · IEEE Trans. Computers 1992

Methods — techniques the papers use, named apart from their topics

two-level pipelining · 0.0coding techniques · 0.0
YearPublicationVenuePosition
1992 Concurrent Error Detection and Correction in Real-Time Systolic Sorting Arrays
abstract
A novel approach to online error detection and correction for high-throughput VLSI sorting arrays is presented. The error model is defined at the sorting element level and both functional errors and data errors are considered. Functional errors are detected and corrected by exploiting inherent properties as well as newly discovered special properties of the sorting array. Coding techniques are used to locate data errors. All the checkers are designed to be totally self-checking and hence the sorting array is highly reliable. Two-level pipelining is employed, making the design very efficient and suitable for real-time application. The structure is very regular and therefore is very attractive for VLSI or WSI implementation.>
Sy-Yen Kuo, Sheng-Chiech Liang
IEEE Trans. Computers2
1991 Efficient Parallel Sorting and Merging Algorithms for Two-Dimensional Mesh-Connected Processor Arrays
Sy-Yen Kuo, Sheng-Chiech Liang
ICPP (3)2
1991 Design and Evaluation of Fault-Tolerant Interleaved Memory Systems
Sy-Yen Kuo, Ahmed Louri, Sheng-Chiech Liang
ICPP (1)3