Clock line control (CLC) is proposed as a new design for testability technique which can transform a complex test generation problem into many small ones that are efficiently manageable by selectively enabling or disabling the synchronous operation of modules. A novel sequential test generation technique for the circuits with CLC scheme is also presented. The new test generation methodology is able to selectively clock modules, expand multiple time frames for a sequential module and compose these local time frames to generate input and clock vectors for an entire circuit. Test generation for the ISCAS'89 circuits, with and without CLC has been performed. Higher fault coverage in a shorter time has been achieved using test generation with CLC.

This paper presents a novel sequential test generation technique for circuits with clock line control (CLC). CLC is a design for testability (DFT) technique that can transform a complex test generation problem into multiple small ones that are efficiently manageable by selectively enabling or disabling the synchronous operation of modules. The new test generation methodology for CLC circuits is smart enough to selectively clock modules, expand multiple time frames for a sequential module and compose these time frames to generate input and clock vectors for an entire circuit. Test generation for the ISCAS '89 circuits, with and without both CLC and scan has been performed. High fault coverage in a short time has been achieved using test generator with CLC.>

A hybrid DFT method is proposed to reduce the hardware penalty of traditional DFT methods and test generation time. It takes advantages of both traditional DFT methods like scan and DFT methods which control clocks for testability. The hardware scheme and test generation algorithm are presented. Test generation results for ISCAS '89 circuits have been generated and showed an improvement in test generation time and fault coverage.

A cost model for and implementation of a hierarchical test generation technique are presented. The cost model is based on fundamental test generation activities such as implication, justification, and backtracking. The model shows that the cost of hierarchical test generation grows as G log G under some realistic assumptions, while the cost of gate-level test generation may grow as fast as G/sup 2/, where G is the number of gates in a circuit under test. This implies that hierarchical test generators should be much faster than flat test generators on large circuits. The implementation of the hierarchical test generation is fan-out-oriented and uses a minimal hierarchical representation of the circuit and functional level heuristics to perform implication, propagation, and backtracing with high-level functional models. Experiments with three hierarchically described circuits show that hierarchical test generation is 1.5 to 8.9 faster than flat gate-level generation.>

A fast algorithm for minimizing the two-level AND/XOR representation of combinational functions, based on a graphical data structure similar to the OBDD, is described. This GMX (Graphical Minimizer for XORs) algorithm works by 'reading-off' and minimizing the solution from an augmented OBDD, called an SFG. The advantage of the SFG structure is that it is often of polynomial size. The algorithm generates solutions significantly better, or no worse, than all previously published solutions on a set of example circuits.>

It is pointed out that advanced submicron CMOS processes result in failure mechanisms that tend to be increasingly analog in nature. They are not adequately covered by stuck-at, stuck-on, or stuck-open models. Furthermore, delay faults, spot defect models, and IDDQ approaches only cover restricted subsets of the dominant failure mechanisms. The impedance fault model forms a superset of all the above fault models while explicitly addressing the analog nature of the failures. An associated design methodology for robust impedance fault testability (DRIFT) provides robustly testable general structures with less area overhead than other transistor level DFT techniques and negligible speed penalties. DRIFT is especially well-suited for gate array, standard cell, and synthesized designs. The effects of process and device level variabilities of the IC are directly represented as variations of the channel impedance characteristics. The DRIFT techniques then transform the channel impedance difference into logic level changes at the CMOS structure output. >

The authors introduce a new deterministic test pattern generation algorithm for sequential circuits. The Sequential Target Switching (STarS) algorithm begins generating a test sequence for a specific target fault, but as each pattern is generated, it keeps track of the set of faults that may also use this sequence as part of a test. Backtracking is avoided by switching the target fault to a member of this fault set, and partial sequences are re-used as much as possible.>

FANHAT, has been designed and implemented to accelerate test generation for digital circuits. FANHAT uses a minimal hierarchical representation of the circuit and functional level heuristics to perform implication, propagation, and backtracking with high-level functional model. Experiments with three circuits show hierarchical test generation using FANHAT is 1.5 to 8.9 times faster than flat gate-level test generation.>

Test generation algorithms use search strategies to control decision making whenever the algorithms encounter a choice of a signal value or action. The authors' study of traditional search strategies used in automatic test pattern generation (ATPG) has led to the observation that no single strategy is superior for all faults in a circuit or all circuits. Further experimentation led to the conclusion that a combination of search strategies provides better fault coverage and/or faster ATPG for a given backtrack limit. Instead of using just one strategy to the backtrack limit, a primary strategy is used for the first half of the backtrack limit, and then a secondary strategy is used for the second half. The authors present an ATPG cost model based on the number of test generation events. They use this model to explain why search strategy switching is faster and show experimental evidence to verify the search strategy switching theory. The experiments were performed with the ISCAS circuits and the authors' implementation of the FAN algorithm.>

This paper presents the technique of concurrent hierarchical fault simulation, a performance model, and two hierarchical optimization techniques to enhance fault simulator performance. The mechanisms for these enhancements are demonstrated with a performance model and are validated experimentally via CHIEFS, the Concurrent Hierarchical and Extensible Fault Simulator, and WRAP, an offline hierarchy compressor. Hieararchy-based fault partitioning and circuit reconfiguration are shown to improve simulator performance to O(n log n) under appropriate conditions. A decoupled fault modeling technique permits further performance improvements via a bottom-up hierarchy compression technique where macros of primitives are converted to single primitives. When combined, these techniques have produced a factor of 180 speedup on a mantissa multiplier. The performance model indicates that the speedup should increase with circuit size.