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Said Amellal

dblp:02/4464 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 1994
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › logic synthesis › formal synthesis
functional synthesis
0.011994
Functional synthesis of digital systems with TASS · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Electronic design automation
high-level synthesis
0.011994
Functional synthesis of digital systems with TASS · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Electronic design automation
logic synthesis
0.011994
Functional synthesis of digital systems with TASS · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Electronic design automation › high-level synthesis
scheduling
0.011994
Functional synthesis of digital systems with TASS · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994

Methods — techniques the papers use, named apart from their topics

tabu search · 0.0penalty-weight formulation · 0.0integer linear programming · 0.0control and dataflow graph · 0.0
YearPublicationVenuePosition
1994 Functional synthesis of digital systems with TASS
abstract
Synthesizing a digital system from a functional description is a complex process requiring the solution of various different problems. TASS (Tabu Search Synthesis System) is a functional synthesis system made up of interdependent modules based on new and more efficient algorithms. First, a control and data flow graph model for system representation is developed and presented. This model generates a single graph representing both the data and control flows of a VHDL behavioral description. A new representation of conditional branches and a mutual exclusion testing procedure offering optimized resource sharing and critical path reduction possibilities have been developed. This graph model is an environment used for various synthesis needs starting from high-level transformations to FSM synthesis for controller implementation. A new mathematical formulation of the scheduling problem is developed using a new approach based on penalty weights. This approach avoids the inflexibility of the ILP formulations developed in related works where the functional unit performing each type of operation is fixed prior to scheduling. The Tabu Search technique, which has been effective in finding optimal solutions for many types of large and difficult combinatorial optimization problems, has been adapted for this purpose. This technique, which performs an intelligent and fast solution space exploration, combined with an effective mathematical formulation makes the scheduling algorithm presented here very powerful.>
Said Amellal, Bozena Kaminska
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
1993 Scheduling of a Control and Data Flow Graph
Said Amellal, Bozena Kaminska
ISCAS1