Quantization of diffusion models has attracted considerable attention due to its potential to enable various applications on resource-constrained mobile devices. However, given the cumulative nature of quantization errors in quantized diffusion models, overall performance may still decline even with efforts to minimize quantization error at each sampling step. Recent studies have proposed several methods to address accumulated quantization error, yet these solutions often suffer from limited applicability due to their underlying assumptions or only partially resolve the issue due to an incomplete understanding. In this work, we introduce a novel perspective by conceptualizing quantization error as a "stepback" in the denoising process. We investigate how the accumulation of quantization error can distort the sampling trajectory, resulting in a notable decrease in model performance. To address this challenge, we introduce StepbaQ, a method that calibrates the sampling trajectory and counteracts the adverse effects of accumulated quantization error through a sampling step correction mechanism. Notably, StepbaQ relies solely on statistics of quantization error derived from a small calibration dataset, highlighting its strong applicability. Our experimental results demonstrate that StepbaQ can serve as a plug-and-play technique to enhance the performance of diffusion models quantized by off-the-shelf tools without modifying the quantization settings. For example, StepbaQ significantly improves the performance of the quantized SD v1.5 model by 7.30 in terms of FID on SDprompts dataset under the common W8A8 setting, and it enhances the performance of the quantized SDXL-Turbo model by 17.31 in terms of FID on SDprompts dataset under the challenging W4A8 setting.

Virtual try-on tasks aim at synthesizing realistic try-on results by trying target clothes on humans. Most previous works relied on the Thin Plate Spline or appearance flows to warp clothes to fit human body shapes. However, both approaches cannot handle complex warping, leading to over distortion or misalignment. Furthermore, there is a critical unaddressed challenge of adjusting clothing sizes for try-on. To tackle these issues, we propose a Clothing-Oriented Transformation Try-On Network (COTTON). COTTON leverages clothing structure with landmarks and segmentation to design a novel landmark-guided transformation for precisely deforming clothes, allowing for size adjustment during try-on. Additionally, to properly remove the clothing region from the human image without losing significant human characteristics, we propose a clothing elimination policy based on both transformed clothes and human segmentation. This method enables users to try on clothes tucked-in or untucked while retaining more human characteristics. Both qualitative and quantitative results show that COTTON outperforms the state-of-the-art high-resolution virtual try-on approaches. All the code is available at https://github.com/cotton6/COTTON-size-does-matter.

The evaluation of participant contribution in federated learning (FL) has recently gained significant attention due to its applicability in various domains, such as incentive mechanisms, robustness enhancement, and client selection. Previous approaches have predominantly relied on the widely adopted Shapley value for participant evaluation. However, the computation of the Shapley value is expensive, despite using techniques like gradient-based model reconstruction and truncating unnecessary evaluations. Therefore, we present an efficient approach called Single-round Participants Amalgamation for Contribution Evaluation (SPACE). SPACE incorporates two novel components, namely Federated Knowledge Amalgamation and Prototype-based Model Evaluation to reduce the evaluation effort by eliminating the dependence on the size of the validation set and enabling participant evaluation within a single communication round. Experimental results demonstrate that SPACE outperforms state-of-the-art methods in terms of both running time and Pearson’s Correlation Coefficient (PCC). Furthermore, extensive experiments conducted on applications, client reweighting, and client selection highlight the effectiveness of SPACE. The code is available at https://github.com/culiver/SPACE.

Windshield images captured by surveillance cameras are usually difficult to be seen through due to severe image degradation such as reflection, motion blur, low light, haze, and noise. Such image degradation hinders the capability of identifying and tracking people. In this paper, we aim to address this challenging windshield images enhancement task by presenting a novel deep learning model based on a two-way generative adversarial network, called Two-way Individual Normalization Perceptual Adversarial Network, TWIN-PAN. TWIN-PAN is an unpaired learning network which does not require pairs of degraded and corresponding ground truth images for training. Also, unlike existing image restoration algorithms which only address one specific type of degradation at once, TWIN-PAN can restore the image from various types of degradation. To restore the content inside the extremely degraded windshield and ensure the semantic consistency of the image, we introduce cyclic perceptual loss to the network and combine it with cycle-consistency loss. Moreover, to generate better restoration images, we introduce individual instance normalization layers for the generators, which can help our generators better adapt to their own input distributions. Furthermore, we collect a large high-quality windshield image dataset (WIE-Dataset) to train our network and to validate the robustness of our method in restoring degraded windshield images. Experimental results on human detection, vehicle ReID and user study manifest that the proposed method is effective for windshield image restoration.

Fast and accurate thermal analysis is crucial for determining the propagation of heat and tracking the formation of hotspots in integrated circuits (ICs). Existing academic thermal analysis tools primarily use compact models to accelerate thermal simulations but are limited to linear problems on relatively simple circuit geometries. The Manchester Thermal Analyzer (MTA) is a comprehensive tool that allows for fast and highly accurate linear and nonlinear thermal simulations of complex physical structures including the IC, the package, and the heatsink. The MTA is targeted for 2.5/3-D IC designs but also handles standard planar ICs. The MTA discretizes the heat equation in space using the finite element method and performs the time integration with unconditionally stable implicit time stepping methods. To improve the computational efficiency without sacrificing accuracy, the MTA features adaptive spatiotemporal refinement. The large-scale linear systems that arise during the simulation are solved with fast preconditioned Krylov subspace methods. The MTA supports thermal analysis of realistic integrated systems and surpasses the computational capabilities and performance of existing academic thermal simulators. For example, the simulation of a processor in a package attached to a heat sink, modeled by a computational grid consisting of over 3 million nodes, takes less than 3 min. The MTA is fully parallel and publicly available.1

Thermal analysis of integrated circuits (IC) is a high performance computing problem because the nanoscale spatiotemporal features of the problem result in a large discrete problem. In previous works, compact models of ICs were introduced to speed up the modeling process. However, such methods have limited accuracy as they approximate the underlying physics. They are also ill-suited to simulate the thermal characteristics of an IC at the cell-level. The finite element method (FEM) is an appropriate computational technique for providing both fast and accurate thermal analyses. Considering that the number of cells in modern ICs is on the order of millions, thermal analysis at this abstraction level is a formidable task. Consequently, handling the computational meshes and computing thermal profiles of an IC at the cell-level requires substantial computing power. In order to provide accurate cell-level thermal simulations at a lower computational cost, this work introduces advanced techniques that judiciously trade off mesh granularity with simulation accuracy which allows fast analysis of cell-level floorplans. The proposed cell-homogenization techniques start with a flat cell-level floorplan and a related power trace and produce reduced order meshes that accelerate thermal simulations with a negligible loss in accuracy. Results show that the proposed techniques achieve up to a 90% reduction in the number of nodes in the mesh with less than 5% error in the temperature compared to the full scale mesh. The simulation time is also reduced by an order of magnitude.

Skyline queries are currently the most notable type of multi-criteria search algorithm. A skyline query returns all of the data points in a given a dataset that are not dominated by other data points. However, this type of query is limited by the fact that the number of results cannot be controlled. In some cases, this can result in an excessive number of results, whereas other cases result in an insufficient number of results. In this study, we propose a scheme referred to as m-representative skyline queries to provide control over the number of results that are returned. We also developed a naive algorithm and a sorted algorithm to provide additional control over the search process. Experiment results demonstrate the efficacy of the proposed approach.

Thermal analysis is crucial for determining the propagation of heat and tracking the formation of hot spots in advanced integrated circuit technologies. At the core of the thermal analysis for integrated circuits is the numerical solution of the heat equation. Prior academic thermal analysis tools typically compute temperature by applying finite difference methods on uniform grids with time integration methods having fixed time step size. Additionally, the linear systems arising from the discretized heat equation are solved using direct methods based on matrix factorizations. Direct methods, however, do not scale well as the problem size increases. Moreover, most of the tools support only 2-D or a limited number of 3-D technologies. To address these issues, this paper presents a novel thermal analyzer with the ability to model both 2-D and 3-D circuit technologies. The analyzer solves the heat equation using the finite element method for the spatial discretization coupled with implicit time integration methods for advancing the solution in time. It also offers fully adaptive spatio-temporal refinement features for improved accuracy and computational efficiency. The resulting linear systems are solved by a multigrid preconditioned Krylov subspace iterative method, which gives superior performance for 3-D transient analyses. The analyzer is shown to accurately capture the propagation of heat in both the horizontal and vertical directions of integrated systems.

A facial sketch synthesis system is proposed, featuring a 2D direct combined model (2DDCM)-based face-specific Markov network. In contrast to the existing facial sketch synthesis systems, the proposed scheme aims to synthesize sketches, which reproduce the unique drawing style of a particular artist, where this drawing style is learned from a data set consisting of a large number of image/sketch pairwise training samples. The synthesis system comprises three modules, namely, a global module, a local module, and an enhancement module. The global module applies a 2DDCM approach to synthesize the global facial geometry and texture of the input image. The detailed texture is then added to the synthesized sketch in a local patch-based manner using a parametric 2DDCM model and a non-parametric Markov random field (MRF) network. Notably, the MRF approach gives the synthesized results an appearance more consistent with the drawing style of the training samples, while the 2DDCM approach enables the synthesis of outcomes with a more derivative style. As a result, the similarity between the synthesized sketches and the input images is greatly improved. Finally, a post-processing operation is performed to enhance the shadowed regions of the synthesized image by adding strong lines or curves to emphasize the lighting conditions. The experimental results confirm that the synthesized facial images are in good qualitative and quantitative agreement with the input images as well as the ground-truth sketches provided by the same artist. The representing power of the proposed framework is demonstrated by synthesizing facial sketches from input images with a wide variety of facial poses, lighting conditions, and races even when such images are not included in the training data set. Moreover, the practical applicability of the proposed framework is demonstrated by means of automatic facial recognition tests.

While traditional Field-Programmable Gate Array design flow usually employs fine-grained tile-based placement, modular placement is increasingly required to speed up the large-scale placement and save the synthesis time. Moreover, the commonly used modules can be pre-synthesized and stored in the library for design reuse to significantly save the design, verification time, and development cost. Previous work mainly focuses on modular floorplanning without module placement information. In this article, we propose a library-based placement and routing flow that best utilizes the pre-placed and routed modules from the library to significantly save the execution time while achieving the minimal area-delay product. The flow supports the static and reconfigurable modules at the same time. The modular information is represented in the B*-Tree structure, and the B*-Tree operations are amended together with Simulated Annealing to enable a fast search of the placement space. Different width-height ratios of the modules are exploited to achieve area-delay product optimization. Partial reconfiguration-aware routing using pin-to-wire abutment is proposed to connect the modules after placement. Our placer can reduce the compilation time by 65% on average with 17% area and 8.2% delay overhead compared with the fine-grained results of Versatile Place and Route through the reuse of module information in the library for the base architecture. For other architectures, the area increase ranges from 8.32% to 25.79%, the delay varies from − 13.66% to 19.79%, and the runtime improves by 43.31% to 77.2%.

FPGA is a promising hardware accelerator in modern high-performance computing systems. In such a system, power is a key factor in the design requiring thermal and energy-saving considerations. Modern power estimators for FPGA either support specific hardware provided by FPGA vendors or contain power models for certain types of conventional FPGA architectures. However, with technology advancement, novel versatile FPGA architectures are introduced to further augment current FPGA architecture, such as emerging FPGA with non-volatile memory, nano-wire interconnection of reconfigurable array, etc. To evaluate the power consumption of various FPGA designs, the power estimator has to be made more flexible and extensible to support new devices and architectures. We introduce a novel power estimator with hierarchical library supporting power models at different levels, e.g. novel circuits of components, emerging memory devices, time-multiplexing architecture etc. The power estimator also supports coarse-grain or fine-grain power estimation defined by users for achieving complexity-accuracy trade-off. Simulation results of benchmarks on the proposed power estimator against commercial estimators demonstrate accuracy of our tool. The proposed tool demonstrates flexibility to estimate power for both existing FPGA architectures and new architectures.

Abstract The skyline search problem has been identified as one of the key problems in database research. None of the developed skyline search algorithms include the use of a filter to facilitate the search process. This paper proposes a novel modification involving the use of skyline filters to reduce the search space of a skyline problem by removing data points that cannot provide a viable skyline result. Three filters based on the concept of neural networks are proposed in this paper. The result is a reduction in execution time achieved through the reduction of the input tuples. The proposed filters may be used in conjunction with any existing skyline search algorithm. This is the first study to apply neural network technology to the skyline problem. Comprehensive simulation results demonstrate the effectiveness of the proposed skyline filtering system.

FPGAs are becoming promising hardware accelerators for high performance computing systems, such as cloud computing, big-data processing, etc., where power is a key factor due to thermal and energy saving considerations. Current CAD tools for FPGA power estimation either support specific hardware provided by vendors or contain power models for mainly conventional FPGA architectures. However, with technology advancement, versatile novel FPGA architectures are being proposed to further augment current FPGA architecture at various aspects, such as emerging FPGA based on non-volatile memory, improved logic and DSP design, etc. In order to evaluate the power consumption of versatile FPGA designs, the power estimator has to be made more flexible and extendable to support new devices and architectures. In this work, we proposed such a tool that the power estimation can be performed based on a hierarchical library which contains power models at different levels, such as circuit components or devices. The tool can collect resource utilization of FPGA for the implemented circuit, and then perform power estimation at coarse-grain or fine-grain levels based on the hierarchical library to achieve the desired complexity-accuracy trade-off. The flexibility is provided that users can customize the hierarchical library for new circuit components or devices with power number of their own study.

With the wide application of FPGAs in adaptive computing systems, there is an increasing need to support design automation for PR FPGAs. However, there is a missing link between CAD tools for PR FPGA and existing widely used CAD tools, such as VPR. Hence, in this work we propose a modular placer for FPGAs because each PR region needs to be identified during partial reconfiguration and treated as an entity during placement and routing, which is not well supported by the current CAD tools. Our proposed tool is built on top of VPR. It takes the pre-synthesized module information from library, such as area, delay, etc, and performs modular placement to minimize total area and delay of the application. Modular information is represented in B*-Tree structure to allow fast placement. We amend the operations of B*-Tree to fit hardware characteristic of FPGAs. Different width-height ratios of the modules are exploited to achieve area-delay product optimization. Experimental results show comparisons of area, delay and execution time with original VPR. Though it may have disadvantage in area because of blank area among modules, it improves the delay of most of benchmarks comparing to results from VPR. At the end, we show PR-aware routing based on the modular placement.

To enhance the system integrity of FPGA-based embedded systems on hardware design, we propose a hardware security scheme for nonvolatile resistive random access memory (RRAM) based FPGA, in which internal block RAM (BRAMs) are used for configuration and temporary data storage. The proposed scheme loads obfuscated configurations into nonvolatile BRAMs to protect design data from physical attacks and utilizes Chip DNA to enable logic function.

Look Up Table (LUT) is a basic configurable logic element in Field Programmable Gate Arrays (FPGAs). In a commercial product, Static Random Access Memory (SRAM) has been widely used in each LUT to store configured logic. Recently, emerging Resistive RAM (RRAM) has attracted a lot of attention for its high density and non-volatility. In this work, we explore a novel LUT design with bipolar RRAM devices. To obtain design efficiency, a 3D high-density interleaved memory structure is introduced in the proposed LUT. The corresponding peripheral circuits were developed with TSMC 0.18µm technology node. Compared to the traditional SRAM-based FPGA, the RRAM-based LUT demonstrates advantages such as a eliminating initialization stage, a much higher density with 56% area reduction, a bit-addressable write scheme, dynamic reconfiguration, and better flexibility in supporting various configurations.

We demonstrates a novel Field-Programmable Gate Array (FPGA) structure based on Resistive Random Access Memory (RRAM) system. RRAM is a non-volatile memory device which is compatible to CMOS Back End of Line (BEOL) process with only 4F2area per cell. We use a 1R system memory for logic element, Look-Up-Table (LUT), with three dimension stacking structure. The proposed 2R memory system is for routing elements, Switch Block (SB) and Connection Block (CB), with Complementary Resistive Switches (CRS) structure. Both three dimension stacking and CRS structure are crossbar-like structure to further improve density of the FPGA. The proposed design is different from modern FPGA with Static Random Access Memory (SRAM) system, RRAM-based FPGA has benefits of non-volatility, smaller area, and flexibility of configuration. A bit-addressable LUT is introduced with function of run-time programming memory cells of LUT, which is also known as Distributed Random Access Memory (D-RAM). Based on our simulation results, 62.7% of area reduction and 34% of delay improvement can be achieved compared to the conventional FPGA.

With rising demands for high-performance computing and design flexibility of post-fabrication system, reconfigurable architecture has been drawing increasing attentions. However, reconfigurability, advantage of current Field-Programmable Gate Array (FPGA), is severely limited by small capacity of on-chip Static Random Access Memory (SRAM) for storing configuration bits. With emerging high-density and high-performance nano memory devices, opportunities are provided to improve the reconfigurability of the current FPGA's design.

Resistive random access memory (RRAM) is a promising candidate to substitute static random access memory (SRAM) in lookup table (LUT) design for its high density and non-volatility. RRAM cells are fabricated at backend CMOS process and have negligible area cost. However, the complex peripheral circuit design to satisfy performance and accuracy requirements becomes a major issue. In this work, we propose a novel peripheral circuit for RRAM-based LUT. A new decoding scheme that supports dynamic programming is introduced. Furthermore, the expanded RRAM crossbar array together with the latch comparator based sense amplifier can dramatically reduce design complexity, decrease area cost, and improve tolerance on process variations. Compared to a 6-input SRAM-based LUT, the proposed RRAM-based one cuts off 60.4% of layout area. The maximal operating frequency reaches 1GHz at 10mV input difference. Simulations also show that the proposed LUT functions properly even RRAM resistances deviates 20% from the design value.

Resistive random access memory (ReRAM) has been demonstrated as a promising non-volatile memory technology with features such as high density, low power, good scalability, easy fabrication and compatibility to the existing CMOS technology. The conventional three-dimensional (3D) bipolar ReRAM design usually stacks up multiple memory layers that are separated by isolation layers, e.g. Spin-on-Glass (SOG). In this paper, we propose a new 3D bipolar ReRAM design with interleaved complimentary memory layers (3D-ICML) which can form a memory island without any isolation. The set of metal wires between two adjacent memory layers in vertical direction can be shared. 3D-ICML design can reduce fabrication complexity and increase memory density. Meanwhile, multiple memory cells interconnected horizontally and vertically can be accessed at the same time, which dramatically increases the memory bandwidth.

This paper presents a Hammerstein-Wiener recurrent neural network with a parameter learning algorithm for identifying unknown dynamic nonlinear systems. The proposed recurrent neural network resembles the conventional Hammerstein-Wiener model that consists of a dynamic linear subsystem embedded between two static nonlinear subsystems. There are two novelties in our network: (1) the three subsystems are integrated into a single recurrent neural network whose output is the nonlinear transformation of a linear state-space equation; (2) the well-developed linear theory can be applied directly to the linear subsystem of the trained network to analyze its characteristics. In addition, we utilized the Stone-Weierstrass theorem to demonstrate the proposed network possesses the universal approximation capability. Finally, a computer simulation and comparisons with some existing models have been conducted to demonstrate the effectiveness of the proposed network and its parameter learning algorithm.

In this paper, we propose two interest-based bandwidth-efficient lookup protocols, simple lookup protocol and advanced lookup protocol, for mobile environments. A peer willing to search files broadcasts a query message with keywords relevant to its interests to its neighbors in the transmission range, and only those neighbors also interested in the query forward. Simulation results show that our protocols have higher success rate and raise the scalability and bandwidth efficiency comparing to the previous work. Besides, our protocols can avoid selfish behaviors, since the behavior of forwarding queries benefits not only the source node but also the forwarding node.

We propose a distributed architecture of Web filtering system focused on its operation and implementation for IPv6 home networks. The realized system, called WKeeper, employs the feature of IPv6 anycast to achieve distributed load balance. WKeeper has been proven to be functioning well in both IPv4 and IPv6 networks even with mobility support. In a home network environment, WKeeper efficiently and precisely maintains the URL-block-list database with enormous amount of entries, as well as its operation is robust and with low cost. Besides, experimental result shows that the delay of query response is bounded significantly even if heavy load.