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Per-Erik Danielsson

dblp:02/4899 · DBLP profile ↗
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21ranked-venue papers
9as first author
0since 2021 · last 2006
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Graphics, computer vision, multimedia, augmented reality and games · 11 · 5 first-authorArtificial intelligence and machine learning · 7 · 3 first-authorSystems, architecture and hardware · 6 · 3 first-authorSoftware engineering, systems software and programming languages · 1Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer graphics and multimedia
3 papers
Image and video processing · 90% Multimedia analysis and retrieval · 9% Audio and music processing · 2%
Computer architecture, parallel and distributed computing, and storage systems
6 papers
Hardware accelerators and domain-specific architectures · 69% Integrated circuit design · 14% Processor architecture and microarchitecture · 10%
Theoretical computer science
2 papers
Computational complexity · 49% Algorithms and data structures · 49% Logic in computer science · 2%

Topics — the 20 heaviest of 22, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Image and video processing › image enhancement › contrast enhancement
histogram equalization
0.011998
Intensity mappings within the context of near-sensor image processing · IEEE Trans. Image Process. 1998
Image and video processing
image enhancement
0.011998
Intensity mappings within the context of near-sensor image processing · IEEE Trans. Image Process. 1998
Image and video processing
industrial inspection
0.011988
Inspection of Printed Circuit Boards by Connectivity Preserving Shrinking · IEEE Trans. Pattern Anal. Mach. Intell. 1988
Image and video processing › mathematical morphology
morphological image processing
0.011988
Inspection of Printed Circuit Boards by Connectivity Preserving Shrinking · IEEE Trans. Pattern Anal. Mach. Intell. 1988
Multimedia analysis and retrieval › image analysis › visual inspection
printed circuit board inspection
0.011988
Inspection of Printed Circuit Boards by Connectivity Preserving Shrinking · IEEE Trans. Pattern Anal. Mach. Intell. 1988
Hardware accelerators and domain-specific architectures
signal processing accelerator
0.011984
Serial/Parallel Convolvers · IEEE Trans. Computers 1984
Integrated circuit design
digital circuit design
0.011983
A Variable-Lengt Shift-Register · IEEE Trans. Computers 1983
Hardware accelerators and domain-specific architectures
image processing accelerator
0.011983
LIPP-A SIMD Multiprocessor Architecture for Image Processing · ISCA 1983
Integrated circuit design › digital circuit design › sequential circuit design
shift register
0.011983
A Variable-Lengt Shift-Register · IEEE Trans. Computers 1983
Processor architecture and microarchitecture › SIMD
SIMD processor
0.011983
LIPP-A SIMD Multiprocessor Architecture for Image Processing · ISCA 1983
Electronic design automation
hardware verification and test
0.011988
Inspection of Printed Circuit Boards by Connectivity Preserving Shrinking · IEEE Trans. Pattern Anal. Mach. Intell. 1988
Computational complexity › boolean function complexity
boolean function evaluation
0.011979
Sequential Evaluation of Boolean Functions · IEEE Trans. Computers 1979
Algorithms and data structures › algebraic computation
expression evaluation
0.011979
Sequential Evaluation of Boolean Functions · IEEE Trans. Computers 1979
Audio and music processing
recursive filters
0.011984
Serial/Parallel Convolvers · IEEE Trans. Computers 1984
Hardware accelerators and domain-specific architectures
systolic array
0.011984
Serial/Parallel Convolvers · IEEE Trans. Computers 1984
Processor architecture and microarchitecture
register file
0.011983
A Variable-Lengt Shift-Register · IEEE Trans. Computers 1983
Processor architecture and microarchitecture
SIMD
0.011983
LIPP-A SIMD Multiprocessor Architecture for Image Processing · ISCA 1983
Integrated circuit design › digital circuit design › sequential circuit design
asynchronous sequential circuits
0.011966
Boolean Memories · IEEE Trans. Electron. Comput. 1966
Integrated circuit design › memory circuit design
boolean memory
0.011966
Boolean Memories · IEEE Trans. Electron. Comput. 1966
Logic in computer science
boolean networks
0.011966
Boolean Memories · IEEE Trans. Electron. Comput. 1966

Methods — techniques the papers use, named apart from their topics

variable threshold voltage · 0.0delay insertion · 0.0shrinking · 0.0pipelined hardware implementation · 0.0connectivity-preserving shrinking · 0.0systolic array · 0.0serial/parallel multiplier · 0.0bit-serial design · 0.0distributed processor topology · 0.0bit-serial processing · 0.0multilevel expression extension · 0.0complementary function evaluation · 0.0boolean net analysis · 0.0algebraic treatment · 0.0
YearPublicationVenuePosition
2006 Handling of Long Objects in Iterative Improvement of Nonexact Reconstruction in Helical Cone-Beam CT
abstract
In medical helical cone-beam CT, it is common that the region-of-interest (ROI) is contained inside the helix cylinder, while the complete object is long and extends outside the top and the bottom of the cylinder. This is the Long Object Problem. Analytical reconstruction methods for helical cone-beam CT have been designed to handle this problem. It has been shown that a moderate amount of over-scanning is sufficient for reconstruction of a certain ROI. The over-scanning projection rays travel both through the ROI, as well as outside the ROI. This is unfortunate for iterative methods since it seems impossible to compute accurate values for the projection rays which travel partly inside and partly outside the ROI. Therefore, it seems that the useful ROI will diminish for every iteration step. We propose the following solution to the problem. First, we reconstruct volume regions also outside the ROI. These volume regions will certainly be incompletely reconstructed, but our experimental results show that they serve well for projection generation. This is rather counter-intuitive and contradictory to our initial assumptions. Second, we use careful extrapolation and masking of projection data. This is not a general necessity, but needed for the chosen iterative algorithm, which includes rebinning and iterative filtered backprojection. Our idea here was to use an approximate reconstruction method which gives cone-beam artifacts and then improve the reconstructed result by iterative filtered backprojection. The experimental results seem very encouraging. The cone-beam artifacts can indeed be removed. Even voxels close to the boundary of the ROI are as well enhanced by the iterative loop as those in the middle of the ROI.
Maria Magnusson Seger, Per-Erik Danielsson, J. Sunnegardh
IEEE Trans. Medical Imaging2
2001 Efficient Detection of Second-Degree Variations in 2D and 3D Images
Per-Erik Danielsson, Qingfen Lin, Qin-Zhong Ye
J. Vis. Commun. Image Represent.1
1998 Segmentation of 3D volumes using second derivatives
abstract
The second derivatives of a 2D or 3D signal is claimed to be of fundamental value for image analysis, segmentation, visualization and many other tasks. But to serve this purpose, the derivative responses at each point must be converted to three features: magnitude, shape, and orientation. This paper presents a recently developed derotation algorithm for this task based on eigenvalues analysis of the Hessian matrix and spherical harmonics. Scale invariance is achieved by combining results from different scale detectors. The algorithm has been successfully implemented and applied to magnetic resonance volume data to segment string-like cerebral vessels, for which case some preliminary experimental results are presented.
Per-Erik Danielsson, Qingfen Lin, Qin-Zhong Ye
ICPR1
1998 Intensity mappings within the context of near-sensor image processing
abstract
In the original near-sensor image processing (NSIP) concept, the intensity level for an individual sensor element is mapped onto the time axis so that the time to reach the threshold is inversely proportional to the intensity. In many cases this is favorable, in some cases there is a need for another mapping between time and intensity. We show that such mappings can be achieved by either inserting delays or by varying the threshold voltage. The result is that to achieve a linear mapping it is much more favorable to use a variable threshold since the processing power of the sensor is then better utilized. An interesting result, when it comes to adaptive mapping, is that the traditionally time consuming operation histogram equalization can be accomplished almost for free in the NSIP concept. We also show that other histogram-based, i.e., data-dependent, mapping can be easily implemented.
Anders Åström, Robert Forchheimer, Per-Erik Danielsson
IEEE Trans. Image Process.3
1997 Finding the Minimal Set of Maximum Disks for Binary Objects
Frederik Nilsson, Per-Erik Danielsson
CVGIP Graph. Model. Image Process.2
1994 Velocity Tuned Generalized Sobel Operators for Multiresolution Computation of Optical Flow
abstract
Optical flow computation may be divided into four processing steps where the first is extraction of image features suitable for flow estimation. Using a generalization of the basic flow constraint it is possible to estimate flow vectors from a set of feature images obtained from the input image sequence. Generalized Sobel operators provide a suitable set of feature extraction operators. The set of five filters up to second order provides good approximations of ideal edge and line detectors. A review of spatial and frequency constraints on optical flow suggests a multiresolution approach to optical flow where the initial feature extractors consists of velocity tuned operators. We show that two-dimensional generalized Sobel operators may be extended to spatio-temporal velocity tuned filters for optical flow estimation. Experimental results compare well to existing methods.>
Mats Gökstorp, Per-Erik Danielsson
ICIP (2)2
1992 High-accuracy rotation of images
Per-Erik Danielsson, Magnus Hammerin
CVGIP Graph. Model. Image Process.1
1990 PASIC. A sensor/processor array for computer vision
abstract
The PASIC prototype chip contains 256*256 photosensors, a linear array of 256 A/D converters, two 256 8-bit shift registers, 256 bit-serial processors, and a 256*256 bit dynamic RAM. It appears to be a viable architecture for low-level vision processing. The processors operate in SIMD model at 20 MHz. To avoid high speed transfer of analog data, an A/D converter in the form of a linear array of comparators is used. The architecture of the processing part conforms to the row parallel output from the A/D-converters. A simple but efficient processor excellently suited to the special VLSI constraints of the sensor was designed. The pitch in the present version of PASIC is 30 mu m and it was possible to fit the A/D-converter circuitry, the shift register, the ALU, and the memory into this narrow slot. A key factor is the unified structure achieved by extending the memory data bus to all other units within the same column. The versatility of the chip is shown using three algorithms: edge detection, shading correction, and histogram-based thresholding. Each is executed in approximately 10 ms.>
Keping Chen, Per-Erik Danielsson, Anders Åström
ASAP2
1990 PASIC: a smart sensor for computer vision
abstract
The processor, A/D converter, sensor integrated circuit (PASIC) prototype chip, which contains 256*256 photosensors, a linear array of 256 A/D converters, two 256 8-b shift registers a 256-bit-serial arithmetic logic unit, and a 256*128-b-dynamic RAM, is presented. It is claimed to be a viable architecture for low-level vision processing. The processors operate in single-instruction multiple-data (SIMD) mode at 20 MHz. When executing an edge-detection algorithm, it is shown that the 256 processors are capable of an output rate of 3 Mpixel/s.>
Keping Chen, Anders Åström, Per-Erik Danielsson
ICPR (2)3
1990 Rotation Invariance in Gradient and Higher Order Derivative Detectors
Per-Erik Danielsson, Olle Seger
Comput. Vis. Graph. Image Process.1
1988 Rotation-invariant operators applied to enhancement of fingerprints
abstract
Rotation-invariant operators of order 0 and 2 are used first to detect and then to enhance lines. The enhancement procedure, suitable for fingerprints, is based on suppression of line responses with an orientation that creates a mismatch with the locally dominating direction of the fingerprint. The rotation-invariant operators also serve as basis functions. By construction they are mutually orthogonal and by proper normalization they form an orthonormal set. At the origin any pattern a(r, phi ) can be expanded or at least approximated by such a set of basis functions.>
Per-Erik Danielsson, Qin-Zhong Ye
ICPR1
1988 Evaluation of methods for shaded surface display of CT-volumes
abstract
Twelve methods are evaluated to analyze an ideal sphere and a real human skull. They are different combinations of principles for detection of the surface to be displayed (gray-value threshold, gradient threshold, and zero-crossing of the second derivative), localizing this surface in space (including both grid-point accuracy and subvoxel accuracy), and finally estimating the direction of the surface normal (from the gradient in the 2-D depth image and from the gradient in the 3-D volume). The best quality is obtained by zero-crossing detection, subvoxel localization, and 3-D gradient orientation.>
Maria Magnusson, Reiner Lenz, Per-Erik Danielsson
ICPR3
1988 Inspection of Printed Circuit Boards by Connectivity Preserving Shrinking
abstract
Two algorithms for visual inspection of printed-circuit boards are presented that perform width checking of conductors and insulators. The first detects the difference between the results of shrinking and connectivity-preserving shrinking (CPS). The second algorithm produces a difference between the original and the shrunk picture. This result is subject to a number of CPS-operations after which errors are easily detected. Both algorithms can be adapted to a suitable level of sensitivity to sharp corners and edge irregularities. A sequential version of CPS is also described which is well suited for hardware implementation in a pipelined structure.>
Qin-Zhong Ye, Per-Erik Danielsson
IEEE Trans. Pattern Anal. Mach. Intell.2
1988 On minimum error thresholding and its implementations
Qin-Zhong Ye, Per-Erik Danielsson
Pattern Recognit. Lett.2
1984 A fast sequential method for polygonal approximation of digitized curves
Karin Wall, Per-Erik Danielsson
Comput. Vis. Graph. Image Process.2
1984 Serial/Parallel Convolvers
abstract
A new type of convolver is presented. This type utilizes a kind of systolic array where the basic cell is mainly a full adder and the basic structure is a serial/parallel multiplier. A new formalism is developed which encompasses the whole family of serial/parallel multipliers. All these designs can be carried over to the design of convolvers since the convolution formula has the same structure on the word level as the multiplier on the bit level. Furthermore, the whole convolver can be embedded in one single uniform bit-serial one-dimensional structure. This extremely pin-saving and VLSI-oriented design can also be used for recursive filters and for 2D signal processing. Programmability (using a structure with varying precision and kernel size) can be traded for simplicity and efficacy. The paper contains comparative discussions of other convolvers; however, actual hardware performance is not given.
Per-Erik Danielsson
IEEE Trans. Computers1
1983 LIPP-A SIMD Multiprocessor Architecture for Image Processing
abstract
LIPP (Linköping Image Parallell Processor) is a multiprocessor system intended mainly for image analysis and image processing but even other computing tasks where large amount of data should be manipulated in forms of matrices, such as weather forecasts or other related problems namely systems of differential equations. The processors within the processor array are of bit-serial type with the capability of directly processing data with wordlengths in the range of 1 bit to 32 bits in one bit increments without time penalty. Bit-serial operation gives the possibility of designing suprisingly fast algorithms. To each processor is a fairly large memory (64 Kbit) associated. A processor can instantly reach 8 neighboring memories through an interconnecting network. The processor array whose size is thought to be 16 by 16 it running in SIMD mode. In this way memory access collisions can be minimized. Image and matrix data are mapped in the memory space so that each memory holds a subimage. We call this mapping distributed processor topology. Because of the memory mapping and interconnection network neighborhood operations such as two dimensional convolution are easily performed.
T. Ericsson, Per-Erik Danielsson
ISCA2
1983 On the efficiency of two-bit link chain-code
Per-Erik Danielsson
Pattern Recognit. Lett.1
1983 A Variable-Lengt Shift-Register
abstract
A new way of implementing the variable-length shift-register function is presented. It utilizes two bidirectional shift registers of length N/2 where N is the maximum length anticipated for any input string.
Per-Erik Danielsson
IEEE Trans. Computers1
1979 Sequential Evaluation of Boolean Functions
abstract
This paper presents methods for iterative evaluation of Boolean expressions suitable, e. g., in sequential search and matching when the input variables appear in sequence. The sum-of-product form is assumed and the clue is to partially compute the values of all products partially for each new variable being defined. It is shown that the additive use of an expression for the complementary function can result in a faster evaluation. The method proves to be extendable to multilevel expressions.
Vojin M. Plavsic, Per-Erik Danielsson
IEEE Trans. Computers2
1966 Boolean Memories
abstract
Conditions for equilibrium states in Boolean nets by delay-free feedback are investigated. The result is a new class of circuits called memories, the simplest member of which is the ordinary set-reset flip-flop. A memory is defined as an asynchronous sequential machine with specific properties. The need for gain in feedback loops and the assumption that each amplifier is a NOT operator make it possible to state two theorems on the equilibrium codes. In algebraic treatment it is shown how to design a memory from a given state assignment. Symmetric Boolean memories include multistable flip-flops but also, for instance, a decadic memory utilizing only five inverters.
Per-Erik Danielsson
IEEE Trans. Electron. Comput.1