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Yan Zhuang 0003

dblp:02/5194-3 · DBLP profile ↗
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2ranked-venue papers
1as first author
2since 2021 · last 2023
0009-0001-7964-8074ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 33% Electronic design automation · 33% Memory systems · 33%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
coarse-grained reconfigurable architecture
0.712023
DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs · DAC 2023
Memory systems › data locality
data reuse
0.712023
DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs · DAC 2023
Electronic design automation › high-level synthesis › memory synthesis
memory partitioning
0.712023
DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs · DAC 2023

Methods — techniques the papers use, named apart from their topics

non-uniform memory partitioning · 0.7mapping algorithm · 0.7elastic FIFOs · 0.7
YearPublicationVenuePosition
2023 DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs
abstract
Coarse-Grained Reconfigurable Arrays (CGRAs) are a promising architecture for data-intensive applications. For parallel data accesses, uniform memory partitioning is usually introduced to CGRA for better pipelining performance. However, uniform memory partitioning not only suffers from a local minimum, but also introduces non-negligible overhead for banking function, which may greatly degrade the performance of CGRA. To this end, this paper introduces non-uniform memory partitioning and proposes a data-reuse-friendly CGRA (DARIC). With well elaborated configurable bank groups cooperated with register chains, elastic FIFOs can be achieved for non-uniform memory partitioning. Based on the resource graph of DARIC, a mapping algorithm supporting path sharing is proposed. Finally, the experimental results show that DARIC can achieve 2.35 × throughput and 2.59 × energy efficiency while having even less area and power overhead, as compared to the state-of-the-art.
Dajiang Liu, Di Mou, Yan Zhuang 0003, Jiaxing Shang, Shouyi Yin
DAC4
2022 Towards High-Quality CGRA Mapping with Graph Neural Networks and Reinforcement Learning
abstract
Coarse-Grained Reconfigurable Architectures (CGRA) is a promising solution to accelerate domain applications due to its good combination of energy-efficiency and flexibility. Loops, as computation-intensive parts of applications, are often mapped onto CGRA and modulo scheduling is commonly used to improve the execution performance. However, the actual performance using modulo scheduling is highly dependent on the mapping ability of the Data Dependency Graph (DDG) extracted from a loop. As existing approaches usually separate routing exploration of multi-cycle dependence from mapping for fast compilation, they may easily suffer from poor mapping quality. In this paper, we integrate the routing explorations into the mapping process and make it have more opportunities to find a globally optimized solution. Meanwhile, with a reduced resource graph defined, the searching space of the new mapping problem is not greatly increased. To efficiently solve the problem, we introduce graph neural network based reinforcement learning to predict a placement distribution over different resource nodes for all operations in a DDG. Using the routing connectivity as the reward signal, we optimize the parameters of neural network to find a valid mapping solution with a policy gradient method. Without much engineering and heuristic designing, our approach achieves 1.57× mapping quality, as compared to the state-of-the-art heuristic.
Yan Zhuang 0003, Dajiang Liu
ICCAD1