There is a renewed interest in low-cost Radio Detection and Ranging (Radar) with the growth in automotive autonomous driving. New System on a Chip (SoC) Field-Programmable Gate Array (FPGA) platforms are now available with onboard Analogue to Digital Converters (ADC)s and Digital to Analogue Converter (DAC)s, making them ideal for Radar processing applications. This is leading to some traditional analogue Radio frequency (RF) electronics being replaced by SoC FPGAs, using a Direct Digital Synthesis (DDS) for frequency ramping. Unfortunately, DDSs also produce unwanted spurious frequencies. In this work we propose an FPGA based Digital Signal Processing / Processor (DSP) processing block for a Frequency Modulated Continuous Wave (FMCW) automotive Radar, implemented on Xilinx's FPGA, with a digitally generated Chirp, replacing a Voltage controlled oscillator (VCO). For the proposed Radar a novel method of linearisation, for pre-calibrating the Chirp and FPGA to perform parallel processing of the reflective signal. The proposed design was implemented using MATLAB Simulink Sysgen / Vivado and synthesised on a Zynq FPGA, together with a high-speed ADC and DDS. The design overcomes the challenge of implementing continuous processing on the FPGA platform itself, replacing traditional analogue electronics. The proposed system uses a novel technique of applying dithering to the DDS only when required, greatly reducing the generation of spurious frequencies during transmitting of the linearised chirp. This is the first known 77 GHz FPGA to use this technique.

Transient current instability is one of the most common faults evident in Pulse Width Modulation (PWM) controlled brushless DC motors. This paper explores the under-developed field of real-time acoustic diagnostics for electrically based faults using consumer grade sensors. Current instabilities produce an audible torque transient on the motor, easily detectable using consumer acoustic sensors; a USB microphone and smartphone in this case. Two time-frequency signal processing techniques, Wavelet Packet Transform (WPT) and Empirical Mode Decomposition (EMD), are used to isolate information pertaining to the fault and are assessed for computational performance. This gives four processed signals to search for instabilities using a peak finding technique. We then compare the performance of each method. With the USB microphone WPT signal correlating the best results (93%), a simplistic logarithmic predictive model is used to estimate the durations for the next experimental run, in real-time. The results prove that readily accessible and affordable consumer acoustic sensors can be used for real-time fault diagnostics with a high degree of accuracy.

Efficient spectrum usage is an issue that has been inviting a lot of interest and research in recent times, due to the omnipresence of wireless technologies all around us. Spectrum sensing is a key step towards efficient spectrum usage. Energy detection is a fast and simple method for spectrum sensing, but the sensing precision is limited by the dependency on a threshold value. This paper reports a novel real time energy detection based spectrum sensing technique using a logistic regression classifier. The implementation is done using USRP and GNU-Radio, and achieves a classification accuracy of 98.6% on a dataset that was collected over commercial FM band.

Quantum-dot cellular automata (QCA) technology is an attractive alternative to CMOS for future digital designs. A powerful attack based on power analysis has become a significant threat to the security of CMOS cryptographic circuits. As there is no current flow in QCA, the power consumption of a QCA circuit is extremely low compared to its CMOS counterpart. Therefore, in this paper an investigation is carried out to ascertain if QCA circuits could be immune to power analysis attacks based on a case study of the Serpent cipher. In comparison to a previous design, the proposed QCA implementation of a sub-module of the Serpent cipher is more efficient in terms of complexity, area and latency. By using an upper bound power model, the first power analysis attack of a QCA cryptographic circuit is presented. Simulation results show that even though the power consumption is low, it can still be correlated with the correct key guess, and all possible subkeys applied to the Serpent sub-module can be revealed in a best case scenario for attackers. The security of practical QCA devices is also discussed and could be greatly improved by applying a smoother clock.

It is generally assumed that group studies are more effective for students than individual studies. The objective of this work in progress is to quantitatively evaluate and analyze the effect of collaborative studies on individual students performance. This effort would help the student stimulate interest in group learning and collaboration along with exposing them towards multiple problem solving approaches while working individually or in groups. This way the students are challenged to use their existing knowledge and approach, and augment it further with the knowledge and approach provided by group partners. While there are several efforts that focus on developing new group learning techniques, we intend to study the efficacy of previously proposed techniques under various test settings for EE and CS courses without significantly diverting from the course framework.

In this work we present a novel probabilistic modeling tool (QCAPro) to estimate polarization error and non- adiabatic switching power loss in Quantum-dot Cellular Automata (QCA) circuits. The tool uses a fast approximation based technique to estimate highly erroneous cells in QCA circuit design. QCAPro also provides an estimate of power loss in a QCA circuit for clocks with sharp transitions, which result in non-adiabatic operations and provides an upper bound of power expended. QCAPro can be used to estimate average power loss, maximum and minimum power loss in a QCA circuit during an input switching operation. This work will provide a good platform for researchers who wish to study polarization error and power dissipation related issues in QCA circuits.

With the goal of building an hierarchical design methodology for quantum-dot cellular automata (QCA) circuits, we put forward a novel, theoretically sound, method for abstracting the behavior of circuit components in QCA circuit, such as majority logic, lines, wire-taps, cross-overs, inverters, and corners, using macromodels. Recognizing that the basic operation of QCA is probabilistic in nature, we propose probabilistic macromodels for standard QCA circuit elements based on conditional probability characterization, defined over the output states given the input states. Any circuit model is constructed by chaining together the individual logic element macromodels, forming a Bayesian network, defining a joint probability distribution over the whole circuit. We demonstrate three uses for these macromodel-based circuits. First, the probabilistic macromodels allow us to model the logical function of QCA circuits at an abstract level - the "circuit" level - above the current practice of layout level in a time and space efficient manner. We show that the circuit level model is orders of magnitude faster and requires less space than layout level models, making the design and testing of large QCA circuits efficient and relegating the costly full quantum-mechanical simulation of the temporal dynamics to a later stage in the design process. Second, the probabilistic macromodels abstract crucial device level characteristics such as polarization and low-energy error state configurations at the circuit level. We demonstrate how this macromodel-based circuit level representation can be used to infer the ground state probabilities, i.e., cell polarizations, a crucial QCA parameter. This allows us to study the thermal behavior of QCA circuits at a higher level of abstraction. Third, we demonstrate the use of these macromodels for error analysis. We show that low-energy state configurations of the macromodel circuit match those of the layout level, thus allowing us to isolate weak points in circuits design at the circuit level itself