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Kentaro Nakahara

dblp:02/6495 · DBLP profile ↗
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4ranked-venue papers
2as first author
1since 2021 · last 2024
0000-0002-4803-7182ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-authorGraphics, computer vision, multimedia, augmented reality and games · 2 · 1 since 2021Artificial intelligence and machine learning · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Hardware accelerators and domain-specific architectures · 44% Hardware reliability and fault tolerance · 37% Reconfigurable computing and FPGAs · 19%
Artificial intelligence
1 paper
Face, body and person analysis · 100%

Topics — the 7 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Computer vision › Face, body and person analysis
face detection
0.112007
A Specialized Processor Suitable for AdaBoost-Based Detection with Haar-like Features · CVPR 2007
Hardware accelerators and domain-specific architectures › vision accelerator
object detection accelerator
0.112007
A Specialized Processor Suitable for AdaBoost-Based Detection with Haar-like Features · CVPR 2007
Hardware accelerators and domain-specific architectures
vision accelerator
0.112007
A Specialized Processor Suitable for AdaBoost-Based Detection with Haar-like Features · CVPR 2007
Hardware reliability and fault tolerance › soft errors
soft error resilience
0.112006
Autonomous-repair cell for fault tolerant dynamic-reconfigurable devices · FPGA 2006
Hardware reliability and fault tolerance
error detection and correction
0.012006
Autonomous-repair cell for fault tolerant dynamic-reconfigurable devices · FPGA 2006
Hardware reliability and fault tolerance
redundancy
0.012006
Autonomous-repair cell for fault tolerant dynamic-reconfigurable devices · FPGA 2006
Hardware reliability and fault tolerance › redundancy › modular redundancy
triple modular redundancy
0.012006
Autonomous-repair cell for fault tolerant dynamic-reconfigurable devices · FPGA 2006

Methods — techniques the papers use, named apart from their topics

haar-like features · 0.1adaboost · 0.1FPGA · 0.1
YearPublicationVenuePosition
2024 Few-shot generative model for skeleton-based human action synthesis using cross-domain adversarial learning
abstract
We propose few-shot generative models of skeleton-based human actions on limited samples of the target domain. We exploit large public datasets as a source of motion variations by introducing novel cross-domain and entropy regularization losses that effectively transfer the diversity of the motions contained in the source to the target domain. First, target samples are divided into patches, which are a set of short motion clips. For each patch, we search for a reference motion from the source dataset that is similar to the patch. Next, in adversarial training, our cross-domain regularization encourages the generated sequences to resemble the reference motion at the patch level. Entropy regularization prevents mode collapse by forcing the generator to follow the distribution of the source dataset. Experiments are performed on public datasets where we utilize three action classes from NTU RGB+D 120 as the target and all data of 60 action classes in NTU RGB+D as the source. Ten samples for each target action class, 30 in total, are selected as target data. The results demonstrate that data augmented with the proposed method improve recognition accuracy by 28 % using a ST-GCN classifier.
Kenichiro Fukushi, Yoshitaka Nozaki, Kosuke Nishihara, Kentaro Nakahara
WACV4
2007 A Specialized Processor Suitable for AdaBoost-Based Detection with Haar-like Features
abstract
Robust and rapid object detection is one of the great challenges in the field of computer vision. This paper proposes a hardware architecture suitable for object detection by Viola and Jones based on an AdaBoost learning algorithm with Haar-like features as weak classifiers. Our architecture realizes rapid and robust detection with two major features: hybrid parallel execution and an image scaling method. The first exploits the cascade structure of classifiers, in which classifiers located near the beginning of the cascade are used more frequently than subsequent classifiers. We assign more resources to the former classifiers to execute in parallel than subsequent classifiers. This dramatically improves the total processing speed without a great increase in circuit area. The second feature is a method of scaling input images instead of scaling classifiers. This increases the efficiency of hardware implementation while retaining a high detection rate. In addition we implement the proposed architecture on a Virtex-5 FPGA to show that it achieves real-time object detection at 30 frames per second on VGA video.
Masayuki Hiromoto, Kentaro Nakahara, Hiroki Sugano, Yukihiro Nakamura, Ryusuke Miyamoto
CVPR2
2006 Autonomous-repair cell for fault tolerant dynamic-reconfigurable devices
abstract
Reconfigurable devices are expected to be utilized in the mission-critical fields such as space development, because a system update and a pseudo-repair can be achieved remotely by reconfiguration. However, conventional reconfigurable devices suffer from memory bit upsets caused by charged particles in space that result in fatal system troubles.This paper proposes an autonomous repair mechanism against configuration upsets for fault-tolerant reconfigurable devices. In proposed architecture, devices consist of 'Autonomous-Repair Cells' with built-in (not reprogrammable) error recovery circuits. Each cell realizes a part of the system's functionality, and guarantees fault tolerance against upset of its own configuration memory. In this paper, four types of Autonomous-Repair Cells are designed and then average lifetime is analyzed. Two of cells are based on TMR (Triple Module Redundancy) and the others are based on EDAC (Error Detection and Correction). In a severe situation where a conventional reconfigurable device with 1Mbit configuration data can achieve only 1-minute average lifetime against configuration upsets, all proposed cells can achieve more than 100 years.
Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura
FPGA1
2006 Fault Tolerant Reconfigurable Device Based on Autonomous-Repair Cells
abstract
Reconfigurable devices are expected to be utilized in the mission-critical fields such as space development, because a system update and a pseudo-repair can be achieved remotely by reconfiguration. However, conventional reconfigurable devices suffer from configuration memory upsets caused by radiation in space. This paper proposes an architecture of a fault-tolerant reconfigurable device based on island-style FPGA. The device consists of "autonomous-repair cells" which repairs these upsets autonomously and dynamically. To determine the architecture, we analyze four autonomous repair techniques of the cell experimentally. Then, optimal autonomous repair techniques are applied to both of programmable logics and cell-to-cell routing resources. Through evaluation, we show that proposed device achieves more than 10 years average lifetime against configuration upsets even in a severe situation such as a satellite orbit
Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura
FPL1