The authors present a byte-interleaving architecture for generating higher-order signals in the synchronous optical network (SONET) digital hierarchy and report on the implementation and system performance results of an experimental 2.488 Gbit/s SONET STS-3c to STS-48 (OC-48) byte multiplexer/scrambler and STS-48 (OC-48) to STS-3c byte demultiplexer/descrambler. The proper operation of the byte multiplexer and demultiplexer has been verified in an OC-48 experiment with a bit error rate (BER) of less than 10/sup -14/. It is shown that the byte-interleaving architecture leads to a simple and modular implementation of higher-rate interfaces (such as OC-192 at 9.95 Gbit/s) using state-of-the-art technologies.>

A ring architecture that uses the asynchronous transfer mode (ATM) virtual path (VP) concept to reduce the SONET ring cost in terms of bandwidth management is discussed. The add-drop multiplexer (ADM) proposed for VP ring architectures can evolve from existing SONET ADMs by replacing the STS-3 termination cards by the ATM STS-3c line cards. Existing standard self-healing schemes and protocol SONET rings can be applied to proposed ATM/SONET VP rings. A case study based on a BCC (Bellcore client company) ring network and the sensitivity analysis suggests that the proposed ATM VP ring architecture may be a cost-effective option for implementing the distributed ring grooming system at the DS 1 level. The proposed VP self-healing rings are not only used to carry existing DS 1 and DS 3 service, but can also be used to more cost-effectively consolidate switches for public-switched services and for SMDS, frame relay, and FDDI in metropolitan areas.>

The authors describe a novel scheme that allows a demultiplexer, a byte aligner, and a frame detection circuit tube to be integrated on one chip without compromising the demultiplexer's performance. A research prototype integrated circuit (IC) that incorporates this scheme was designed to operate at speeds up to the SONET STS-48 (synchronous transport signal level 48) rate of 2.488 Gb/s. The IC is implemented in GaAs enhancement/depletion mode MESFET technology, and it performs 1:8 demultiplexing, byte alignment, and SONET frame detection functions. A separate IC that performs 8:1 multiplexing was also implemented using the same technology. The bit error rate; test results show that the multiplexer and demultiplexer with frame detector can operate at 2.488 Gb/s with a bit error rate less than 1*10/sup -14/. Both ICs were tested at data rates up to 3 Gb/s.>