Input/Output (IO) peripherals like storage devices and network interface cards play a significant role in determining the end user visible performance of many server applications. In addition, many server applications depend on accelerators to achieve the desired performance levels. PCIe is the de-facto standard used for connecting IO peripherals and accelerators to server processor System On Chips (SoC). Therefore, it is important to verify that PCIe interface(s) of a server processor SoC allows full utilization of the available PCIe link bandwidth with reasonable transaction latencies for PCIe traffic patterns corresponding to the most common ways in which PCIe IO devices and accelerators are used by applications. Currently, to the best of our knowledge, such IO and accelerator usage model based PCIe interface performance verification can only be done after the manufactured SoC is available (i.e., in post-silicon). Unfortunately, doing such verification in post-silicon means that if any serious performance issues are found, the SoC developer is forced to invest in costly rectification and remanufacturing of the SoC. In this paper, we introduce an emulation-based framework that enables a “shift-left” of usage model based PCIe interface performance verification from post-silicon to pre-silicon. In contrast to the current post-silicon-based approach, our framework offers a low cost, fast turnaround method to identify and fix PCIe related performance issues prior to manufacturing the chip.

Low Power design has traditionally been the area of Implementation engineers. However, with more and more advanced SOCs having to adopt aggressive Power Management techniques, the verification of these architectures has become an explosive problem. This talk will focus on the basic technology shifts required in the arena of verification - in dynanamic, static and formal analysis, in the area of Verification Methodology, Languages and Protocols and in next generation automation flows. The talk will also highlight some of the unsolved problems of today's technology and potential areas for research/collaboration between academia and industry.

No abstract available.

Few would disagree that verification takes the lion's share of today's project resources. If we examine the available research, we quickly discover that verification is a significant pain point that consumes massive amounts of time and resources across a multitude of market segments. Per Gary Smith at Gartner Dataquest, verification consumes 30% to 70% of total schedule, depending on design size. According to Collett International Research, Inc., a majority of ASICs and integrated circuits (ICs) require at least one respin with 71% of respins are due to functional bugs "verification should have caught".With such statistics, it is easy to understand why many contend that the verification challenge is growing at a double exponential rate (that is, exponential with respect to Moore's law). Given verification's importance and its significant impact on fundamental design quality and time-to-market demands, what is our industry doing in response? This panel explores where the methodology highway is taking us - is the destination heaven or just another level of Dante's inferno?Respected authors and experts in verification methodology will share their insights and opinions of the two methodologies used today: verify-after-the-fact (traditional) and verify-as-you-design (emerging). For decades, simulation has necessitated a verify-after-the-fact methodology and yet we can see from the industry research that a high percentage of silicon requires respins. With the latest advances in simulation testbenches and languages, can the verify-after-the-fact approach scale? Or, is it time for a move to a higher level of abstraction that enables a verify-as-you-design methodology.Industry leading chip and systems companies will discuss the methodologies they employ today to address the enormous challenge of functional verification. Questions to be addressed by our esteemed panelists include: How can we bring in schedules? What can we do to increase design quality? What cultural and organizational changes have to take place to bring quality back to the forefront of design? Where is the measurable proof of quality? What are the questions that managers should be asking themselves? What are the engines being used? What formal techniques deliver the greatest success? How important is HW/SW verification? What are the processes or methodologies being used to overcome tool or technology limitations? What is the value of assertions? How does a geographically dispersed engineering team impact design quality? What are the metrics being used to measure progress and success? And how do you know when you are done?Today we currently don't design quality in - we TEST it in (using simulation). But, what would happen if quality was designed in from the beginning? How much could we improve the overall quality level and reduce verification time, and what would this take to do it? Finally, can migration to a new methodology be the highway out of verification hell?

As the popularity of reusing existing designs--or Intellectual Property (IP)--continues to grow, design challenges escalate. The most time-consuming and critical part of IP design and reuse is verifying that it will work as it was designed to and as the user intends. Designers are pushing the limits of IP for new, distinctive and innovative applications. With this innovation come problems that need creative solutions. Product verification, for example, will become more and more important in ensuring the correctness of the design. Over the years, various solutions have come on the market, all seemingly useful, but none reducing the time or manpower it takes to verify the design. With designs becoming increasingly more complex with each new project and verification consuming up to 70 percent of a design cycle, something must be done to alleviate the bottleneck.

This paper describes a functional hardware verification methodology for ASIC intensive products. It spans the ASIC, board, and system level, enabling simulation of the design concurrent with ASIC and board development. The simulation strategy relies on rapid development of behavioural models of ASICs to enable work to proceed in parallel and to achieve the necessary simulation efficiency. The results from a project on which the methodology was used are presented. The process provided early visibility of over 200 issues in the system of which 32 were critical to the successful conformance and timely completion of the project.