Demo Data from VLDB 2026 / reviewers in the wild / expert
Le Baron O. Ferguson
dblp:02/697
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 1986
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Parallel and multicore computing · 44% Interconnection networks and networks-on-chip · 44% Processor architecture and microarchitecture · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing › multiprocessor system
dataflow multiprocessor |
0.0 | 1 | 1986 | Graph Allocation in Static Dataflow Systems · ISCA 1986 |
Interconnection networks and networks-on-chip
hypercube network |
0.0 | 1 | 1986 | Graph Allocation in Static Dataflow Systems · ISCA 1986 |
Processor architecture and microarchitecture
pipelining |
0.0 | 1 | 1986 | Graph Allocation in Static Dataflow Systems · ISCA 1986 |
Methods — techniques the papers use, named apart from their topics
graph partitioning · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1986 | Graph Allocation in Static Dataflow SystemsabstractOne of the most important considerations for a dataflow multiprocessor is the algorithm by which the nodes of a program graph are allocated for execution to its processors. In the case of the static type of architecture one must consider pipelining as well as spatial concurrency. This paper uses a graph partitioning scheme to aid in the design of such algorithms and selection of the associated interconnection topology. The scheme first refines the usual dataflow program graph and then partitions it into “trees.” Our study shows that the hypercube interconnection accommodates these trees in a way that allows as to develop an algorithm that places producer nodes (of a dataflow graph) nears their consumers to keep the message path very short. The algorithm achieves concurrency in simultaneous execution of subgraphs that involve parallel operations, e.g., array operations, and subgraphs that are highly iterative or recursive. An analytical model is given to evaluate the performance of the algorithm. Yang-Chang Hong, Thomas H. Payne, Le Baron O. Ferguson |
ISCA | 3 |
| 1985 | An Architecture for a Dataflow Multiprocessor
Yang-Chang Hong, Thomas H. Payne, Le Baron O. Ferguson |
ICPP | 3 |