On many-core chip designs, short, often-multicast, latency-critical messages, used extensively in high-level coherence and synchronization protocols, often become the bottleneck of parallel performance scaling. This paper presents Spectrum, a hybrid nanophotonic-electric on-chip network that optimizes both throughput and latency. Spectrum's novel planar nanophotonic subnetwork broadcasts latency-critical messages through a wavelength-division multiplexed (WDM) two-dimensional waveguide. Spectrum's throughput-optimized packet-switching electrical subnetwork handles high bandwidth traffic. Overall, Spectrum delivers an almost ideal CMOS-compatible interconnection network for many-core systems.

On-chip communication, including short, often-multicast, latency-critical coherence and synchronization messages, and long, unicast, throughput-sensitive data transfer, limits the power efficiency and performance scalability of many-core chip-multiprocessor systems. This article presents Iris, a CMOS-compatible high-performance low-power nanophotonic on-chip network. Iris' linear-waveguide-based throughput-optimized circuit-switched subnetwork supports throughput-sensitive data transfer. Iris' planar-waveguide-based WDM broadcast-multicast subnetwork optimizes latency-critical traffic and supports the circuit setup of circuit-switched communication. Overall, the proposed design delivers an on-chip communication backplane with high power efficiency, low latency, and excellent throughput.