The integration of Non-Terrestrial Networks (NTN) and Terrestrial Networks (TN) is a promising solution for 6 G, enabling seamless and ubiquitous connectivity by combining the high data rate capabilities of TN with the extensive coverage of NTN. Spectrum sharing between NTN and TN can significantly improve spectral efficiency but poses challenges related to intersystem interference, especially in fast time-varying NTN channels caused by low Earth orbit (LEO) satellite movement. This paper introduces a novel robust spectrum sharing mechanism that addresses these challenges by dynamically adapting to channel variations and mitigating interference in NTN uplink scenarios. Unlike previous approaches, our method independently manages spectrum sharing mechanisms for NTN and TN, reducing coordination complexity and enhancing system adaptability. By leveraging adaptive bandwidth allocation based on real-time channel conditions, the proposed method ensures efficient radio resource utilization and robust performance. Simulation results show that the robust spectrum sharing mechanism achieves up to a 20% improvement in throughput compared to baseline methods, demonstrating its effectiveness in enabling efficient and robust spectrum sharing for NTN-TN integrated networks.

This paper describes a video coding technology proposal submitted by MediaTek in April 2018 in response to a joint call for proposals (CfP) issued by ITU-T VCEG and ISO/IEC MPEG. The proposal uses the conventional block-based hybrid coding approach with a breakthrough design of block structure, substantial improvements of coding tools, and new inventions of loop filtering techniques. First, the block structure is designed using a highly flexible partitioning scheme, where each coding tree unit in a picture is split into multiple coding units (CUs) by a recursive quaternary tree followed by a recursive binary-ternary tree. The prediction unit (PU) and transform unit (TU) concepts are unified with the CU concept, i.e., PU and TU are basically the same as CU. Moreover, inter prediction, intra prediction, transform, quantization, in-loop filtering, and entropy coding are all improved. Finally, new loop filtering techniques are invented, where the proposed convolutional neural network loop filtering is of particular interest. The proposed video codec achieves 43.81% average bit rate savings based on objective measures compared to the High Efficiency Video Coding (HEVC) anchors and is among the best-performing CfP responses both objectively and subjectively. It has been partially adopted into the working draft of the Versatile Video Coding (VVC) standard.

A 4K and Main-10 HEVC video decoder LSI is fabricated in a 28nm CMOS process. It adopts a block-concealed processor (BcP) to improve the visual quality and a bandwidth-suppressed processor (BsP) is newly designed to reduce 30% and 45% of external data accesses in playback and gaming scenario, respectively. It features fully core scalable (FCS) architecture which lowers the required working frequency by 65%. A 10-bit compact scheme is proposed to reduce the frame buffer space by 37.5%. Moreover, a multi-standard architecture reduces are by 28%. It achieves 530Mpixels/s throughput which is two times larger than the state-of-the-art HEVC design [2] and consumes 0.2nJ/pixel energy efficiency, enabling real-time 4K video playback in Ultra-HD Blu-ray player and TV systems.

A 3D Blu-ray-compliant multimedia processor integrating video decoder, display and graphic engines is presented. To cope with the bandwidth/cost-starved Blu-ray system, this design exploits the time-sharing techniques, leading to 31.3% and 29.1% of area reduction in display and decoder parts. Moreover, a graphic and on-screen-display hardwired handshake effectively reduces the DRAM space by 40%. A smart graphic command removal eliminates the redundant memory accesses by 14%. For 3D Blu-ray playback requirements, stereo full-HD video decoding, 24Hz display, and stereoscopic graphic UI are realized under the frequency of 333MHz, 148MHz, and 333MHz, respectively. This test chip is fabricated in 40nm CMOS process with core area of 3.92mm2and power dissipation of 124.1mW.

A first-reported, sub-mW/fps/view multi-view video decoder chip fully compliant to 3D Blu-ray specifications is reported. It explores the resource sharing so as to integrate not only single-view MPEG-2/VC-1/AVC but multi-view MVC standards into a single die. Moreover, it features pipeline management and clock management units so as to improve the processing throughput and clock power efficiency. A test chip for not only single-view video but multi-view H.264/MVC decoding has been designed and fabricated using 40nm 1P7M CMOS process with core area 1.22mm2. Core power dissipation is about 46.5mW under 1920×1080 resolution of single view 60fps or stereo-view 30fps.

A diagnosis technique based on delay testing has been developed to map the severity of process variation on each cell/interconnect delay. Given this information, we demonstrate a post-silicon tuning method on row voltage supplies (inside a chip) to restore the performance of failed chips. The method uses the performance map to set voltages by either pumping up the voltage on cells with worse delays or tuning down on fast cells to save power. On our test cases, we can correct up to 75% of failed chips to pass performance tests, while maintaining less than 10% increase over nominal power consumption.

Wireless sensor networks attract more and more attention since they are capable of monitoring the environment. Since wireless sensor nodes typically have limited energy and power, power efficiency is a main concern in designing protocols for wireless sensor networks. Data aggregation is one of the strategies that can reduce the power consumption in wireless sensor networks. In this paper, we propose a cross layer algorithm with data aggregation to minimize the power consumption. Most importantly, our proposed algorithm is distributed and therefore, it is suitable for wireless sensor networks. From numerical results, we conclude that not all data packets should be aggregated before they arrive the destination nodes.

The capacity of a power controlled wireless network can be changing due to user's mobility, fading or shadowing effects. As a result, the quality of service (QOS) of all users may not be guaranteed in a wireless network. In this paper, we propose a two-phase distributed subset selection algorithm to identify a subset of wireless users whose QOS is guaranteed. In the first phase, it finds a basic feasible set, and then it tries to expand the basic feasible set in the second phase. Through simulations we evaluate the performance of the proposed scheme in terms of the number of average feasible links and the average execution time.

A 124 MSamples/s JPEG 2000 codec is implemented on a 20.1 mm2die with 0.18 mum CMOS technology dissipating 385 mW at 1.8 V and 42 MHz. This chip is capable of processing 1920times1080 HD video at 30 fps. For previous works, the tile-level pipeline scheduling is used between the discrete wavelet transform (DWT) and embedded block coding (EBC). For a tile with size 256times256, it costs 175 kB on-chip SRAM for the architectures using on-chip tile memory or costs 310 MB/s SDRAM bandwidth for the architectures using off-chip tile memory. In this design, a level-switched scheduling is developed to eliminate tile memory and the DWT and the EBC are pipelined at pixel-level. This scheduling eliminates 175 kB on-chip SRAM and 310 MB/s off-chip SDRAM bandwidth. The level-switched DWT (LS-DWT) and the code-block switched EBC (CS-EBC) are developed to enable this scheduling. The codec functions are realized on an unified hardware, and hardware sharing between encoder and decoder reduces silicon area by 40%

This paper presents a word-level decoding architecture of embedded block coding in JPEG 2000. This architecture decodes one coefficient per cycle based on the proposed word-level decoding algorithm. This algorithm eliminates state variable memories by decoding all bit-planes in parallel. The proposed column- switching scan order overcomes intra bit-plane dependency and inter bit-plane dependency to enable parallel processing. Implementation results show that the proposed architecture is capable of decoding 54 MSamples/s at 54 MHz, which can support HDTV 720p (1280 times 720, 4:2:2) decoding at 30 frames/s.

This paper presents a word-level decoding architecture of Embedded Block Coding (EBC) in JPEG 2000. This architecture decodes one coefficient per cycle based on the proposed word-level decoding algorithm. This algorithm eliminates state variable memories by decoding all bit-planes in parallel. The proposed column-switching scan order overcomes intra bit-plane dependency and inter bit-plane dependency to enable parallel processing. Implementation results show the proposed architecture can decode 54 MSamples/s at 54 MHz, which can support HDTV 720p (1280 × 720, 4:2:2) decoding at 30 frames/sec in real time.

The capacity of a power controlled wireless network can be changing due to user’s mobility, fading or shadowing effects. As a result, the quality of service (QOS) of users accepted by call admission control may not be guaranteed in a wireless network. In this paper, we propose a two-phase distributed scheduling algorithm to identify a subset of wireless users whose QOS is guaranteed. In the first phase, each link transmits with a probing power and each user determines whether it can be a member of the basic feasible set or not in a distributed manner. In the second phase, we develop a generalized call admission control algorithm that attempts to merge as many as possible the rest links into the basic feasible set. We consider a variation that attempts to enlarge the set of feasible links. For starvation prevention, we discuss conflict resolution in the power domain and in the time domain. Through simulation we evaluate the performance of the proposed scheme in terms of average execution time, average packet delay and maximum of the cycle time.

In this paper, the scalable architecture of the embedded block coding (EBC) in JPEG 2000, the bit-plane parallel EBC, is proposed. We provided the analysis and an unified design methodology for the bit-plane parallel EBC architecture. To design the bit-plane parallel EBC, there exists three critical difficulties. To overcome the difficulties, three algorithms are proposed. By use of the proposed algorithms, the external bandwidth of the EBC is reduced by 55% averagely, and the throughput of a 4 bit-planes parallel EBC is higher than a word-level EBC with 10 bit-plans parallel by 1.5 times at the bitrate of 1 bits per pixel.

In this paper, a precompression quality-control algorithm is proposed. It can greatly reduce computational power of the embedded block coding (EBC) and memory requirement to buffer bit streams. By using the propagation property and the randomness property of the EBC algorithm, rate and distortion of coding passes is approximately predicted. Thus, the truncation points are chosen before actual coding by the entropy coder. Therefore, the computational power, which is measured with the number of contexts to be processed, is greatly reduced since most of the computations are skipped. The memory requirement, which is measured with the amount required to buffer bit streams, is also reduced since the skipped contexts do not generate bit streams. Experimental results show that the proposed algorithm reduces the computational power of the EBC by 80% on average at 0.8 bpp compared with the conventional postcompression rate-distortion optimization algorithm. Moreover, the memory requirement is also reduced by 90%. The average PSNR degrades only about 0.1-0.3 dB, on average.

The memory issue is the most critical problem for a high performance JPEG2000 architecture. The tile memory occupies more than 50% of the area in conventional JPEG2000 architectures. To solve this problem, we propose a stripe pipeline scheme. For this scheme, a level switch discrete wavelet transform (LS-DWT) and a code-block switch embedded block coding (CS-EBC) are proposed. With small additional memory, the LS-DWT and the CS-EBC can process multiple levels and code-blocks in parallel by an interleaved scheme. As a result, the overall memory requirements of the proposed architecture can be reduced to only 8.5% compared with conventional architectures.

In this paper we study the quality of service of integrated voice and data services in a wireless network. The voice traffic is transmitted in circuit-switched mode and data traffic is transmitted in packet-switched mode. We apply a fluid analysis to study the performance of the data buffer under two handoff schemes and the basic system. From this, analysis, we derive admission controls for voice traffic as well as for data traffic. This analysis also enables us to conclude that the reserved channel scheme not only is more effective in reducing the forced termination probability of handoff calls, it is also more effective in providing the QoS guarantee for the data traffic.