Differential flip-flop designs for high-speed operations are evaluated for single-event (SE) effects using circuit-level simulations. Results show input dependent SE performance of some differential flip-flop designs. Radiation hardenings by layout optimization for all differential flip-flops and by circuit design for SSTC are discussed.

A statistical switch-level simulator, based on interval and statistical analysis techniques, that simulates the effects of fabrication process fluctuations and environmental effects on digital CMOS integrated circuits is presented. The simulator is computationally very cost-effective compared to conventional Monte Carlo simulators, yet produces results with equal accuracy. The simulator enables analysis of the sensitivity of critical function and performance levels to a variety of parameter variations, thus providing a basis for establishing correspondence between process control, yield, and reliability.>

The effects of radiation exposure on the performance of CMOS integrated circuits are difficult to predict and to simulate due to the bias-dependent device parameter shifts. Simulation methodologies for identification of failure mechanisms and performance estimation are developed. These simulation algorithms are implemented in the PARA simulator for switch-level simulation of radiation effects. Simulation results for test circuits are presented that prove that accurate estimations are possible without CPU-intensive simulation programs.>