A majority of parallel applications executed on HPC clusters use MPI for communication between processes. Most users treat MPI as a black box, executing their programs using the cluster's default settings. While the default settings perform adequately for many cases, it is well known that optimizing the MPI environment can significantly improve application performance. Although the existing optimization tools are effective when used by performance experts, they require deep knowledge of MPI library behavior and the underlying hardware architecture in which the application will be executed. Therefore, an easy-to-use tool that provides recommendations for configuring the MPI environment to optimize application performance is highly desirable. This paper addresses this need by presenting an easy-to-use methodology and tool, named MPI Advisor, that requires just a single execution of the input application to characterize its predominant communication behavior and determine the MPI configuration that may enhance its performance on the target combination of MPI library and hardware architecture. Currently, MPI Advisor provides recommendations that address the four most commonly occurring MPI-related performance bottlenecks, which are related to the choice of: 1) point-to-point protocol (eager vs. rendezvous), 2) collective communication algorithm, 3) MPI tasks-to-cores mapping, and 4) Infiniband transport protocol. The performance gains obtained by implementing the recommended optimizations in the case studies presented in this paper range from a few percent to more than 40%. Specifically, using this tool, we were able to improve the performance of HPCG with MVAPICH2 on four nodes of the Stampede cluster from 6.9 GFLOP/s to 10.1 GFLOP/s. Since the tool provides application-specific recommendations, it also informs the user about correct usage of MPI.

SUMMARY To accelerate scientific discovery, the Extreme Science and Engineering Discovery Environment (XSEDE) aims to enhance researcher productivity, increase its user base, and prepare new generations of researchers to use advanced digital technologies. Accordingly, XSEDE is educating diverse populations of new users through regional workshops targeted at large populations of those traditionally underrepresented in the use of XSEDE resources. The expanded scale and scope of recent workshops provide evidence that (1) there is strong interest in leveraging advanced digital services in research and teaching at minority‐serving institutions; (2) these local events are needed to reach these communities; and (3) increased collaboration is required to inculcate the use of computational methods into research and teaching at these institutions. This makes it clear that XSEDE's efforts are meaningful beyond just providing training in advanced digital services; they contribute to national goals for developing and sustaining a large and diverse STEM workforce. This paper focuses on the first of the larger workshops (held at The University of Texas at El Paso) and its impact on subsequent events. Best practices used to plan, execute, and evaluate this workshop are discussed, and the results of a professional assessment of the three workshops are presented. Copyright © 2014 John Wiley & Sons, Ltd.

Providing differentiated service in a consolidated storage environment is a challenging task. To address this problem, we introduce FAIRIO, a cycle-based I/O scheduling algorithm that provides differentiated service to workloads concurrently accessing a consolidated RAID storage system. FAIRIO enforces proportional sharing of I/O service through fair scheduling of disk time. During each cycle of the algorithm, I/O requests are scheduled according to workload weights and disk-time utilization history. Experiments, which were driven by the I/O request streams of real and synthetic I/O benchmarks and run on a modified version of DiskSim, provide evidence of FAIRIO's effectiveness and demonstrate that fair scheduling of disk time is key to achieving differentiated service. In particular, the experimental results show that, for a broad range of workload request types, sizes, and access characteristics, the algorithm provides differentiated storage throughput that is within 10% of being perfectly proportional to workload weights, and, it achieves this with little or no degradation of aggregate throughput. The core design concepts of FAIRIO, including service-time allocation and history-driven compensation, potentially can be used to design I/O scheduling algorithms that provide workloads with differentiated service in storage systems comprised of RAIDs, multiple RAIDs, SANs, and hypervisors for Clouds.

Volunteer computing projects supported by BOINC have been exploring new research directions. For example, mature projects like Folding@home are moving towards the use of a broader range of architectures and computers. Other projects such as Docking@Home are exploring multi-scale, resource-driven and application-driven adaptations of the volunteer system. This paper presents results that enforce the need for knowledge-constructed capabilities in volunteer computing projects, i.e., the capability to drive simulations based on application-results and resource-status. The Docking@Home project, which uses volunteer resources to study putative drugs by computationally simulating the behavior of small molecules (ligands) when docking to a protein, serves as a case study to positively assess two key hypotheses. The first hypothesis claims that the adaptive selection of computational models for docking simulations based on the features of the protein and ligand can positively affect the final accuracy of the prediction. The second hypothesis claims that the adaptive selection of volunteer resources can ultimately improve project throughput.

Virtualized storage systems are required to service concurrently executing workloads, with potentially diverse data delivery requirements, that are running under multiple operating systems. Although a number of algorithms have been developed for I/O performance virtualization among operating system (OS) instances and their applications, none results in absolute performance virtualization. By absolute performance virtualization we mean that the performance experienced by applications of one operating system does not suffer due to variations in the I/O request stream characteristics of applications of other operating systems. Key requirements of I/O performance virtualization are fairness and performance isolation. In this paper, we present a novel virtual I/O scheduler (VIOS) that provides absolute performance virtualization by being fair in sharing I/O system resources among operating systems and their applications, and provides performance isolation in the face of variations in the characteristics of I/O streams. The VIOS controls the coarse grain allocation of disk time to the different operating system instances and is OS independent; optionally, a set of OS-dependent schedulers may determine the fine-grain interleaving of requests from the corresponding operating systems to the storage system.

An I/O system using a sharing model provides concurrently executing applications shared access to the underlying I/O resources. Although the existing sharing models of these I/O systems are purported to be fair, none of them results in performance isolation. Failing to provide performance isolation results in unpredictable application performance. Unpredictability in application performance hampers providing quality of service guarantees. In this paper, we present a formal analysis of the fairness properties of various disk scheduling algorithms and an experimental evaluation of their performance isolation properties. We show that none of the existing "fair" scheduling algorithms provides performance isolation

Several scientific projects use BOINC (Berkeley Open Infrastructure for Network Computing) to perform largescale simulations using volunteers' computers (workers) across the Internet. In general, the scheduling of tasks in BOINC uses a First-Come-First-Serve policy and no attention is paid to workers' past performance, such as whether or not they have tended to perform tasks promptly and correctly. In this paper we use SimBA, a discrete-event Simulator of BOINC Applications, to study new threshold-based scheduling strategies for BOINC projects that use availability and reliability metrics to classify workers and distribute tasks according to this classification. We show that if availability and reliability thresholds are selected properly, then the workers' throughput of valid results increases significantly in BOINC projects.

Often parallel scientific applications are instrumented and traces are collected and analyzed to identify processes with performance problems or operations that cause delays in program execution. The execution of instrumented codes may generate large amounts of performance data, and the collection, storage, and analysis of such traces are time and space demanding. To address this problem, this paper presents an efficient, systematic, multi-step methodology, based on hierarchical clustering, for analysis of communication traces of parallel scientific applications. The methodology is used to discover potential communication performance problems of three applications: TRACE, REMO, and SWEEP3D.

This paper presents initial research on unification of methods for verification and validation (V&V) of software systems. The synergism among methods for V&V are described. The requirements for a unification are defined. The initial steps of a case study of application of the unified approach to V&V is sketched including definition of the problem domain, the approach and some details of a property specification language. An undergraduate course introducing the unified approach to V&V is described. The relationship of this research to other efforts toward unification of V&V are discussed.

SimBA (Simulator of BOINC Applications) is a discrete event simulator that accurately models the main functions of BOINC, a master-worker runtime framework. SimBA generates, distributes, and monitors tasks executed in a highly volatile, heterogeneous, and distributed environment such as Volunteer Computing (VC). In addition, it collects and validates results of executed tasks.To understand the strengths and weaknesses of BOINC under distinct scenarios, project designers must study and quantify its performance without affecting the VC community. Although this is not possible on production systems, it is possible using SimBA, which is capable of testing a wide range of hypotheses in a short period of time.Our experience to date indicates that SimBA is a reliable tool for performance prediction of VC projects. Preliminary results show that SimBA's predictions of [email protected] performance are within approximately 5% of the performance reported by this BOINC project.

Global computing uses Internet-connected PCs volunteered by their owners. These PCs are diverse, volatile, and error-prone. Sophisticated scheduling methods commonly applied in grid computing may not be sufficiently scalable and flexible for global computing environments. This paper shows that it is possible to classify global computing hosts based on simple metrics such as availability and reliability, and that it is efficient to assign tasks to such hosts accordingly. The proposed classification of workers is applied to P@H, a global computing project for protein structure prediction

Shari Lawrence Pfleeger The precipitous decline in women's enrollment in computer science since 1984 has to be addressed in new and creative ways. We must broaden our horizons and think of our students not only as potential compiler or operating systems designers but also as implementers of computerbased solutions to non-computing problems. There is a general trend, among women as well as men, to want to apply computing skills to a wide variety of disciplines outside the traditional software businesses. (Washington Post, 16 August 2000, Business section, p. 1). We can leverage this interest not by watering down our computer science curricula but by strengthening them and adding internships and team projects that apply skills to these outside disciplines. With such a program, a woman interested in finance might be attracted to a CS degree that enables her to intern at a brokerage house, bank, or insurance company, for example. Thus, we can expand from a degree in computing for computing's sake to computing and its place in the wider world. Such an approach appears to be successful in the UK, where departments of computing offer specializations in computer science, information science, and software engineering, often in partnership with industries that provide internships or support for team projects.

The benefits of working in a research group are clear: students develop domain expertise, gain an understanding and appreciation of the research process and its practice, and acquire team, communication, problem-solving, and higher-level thinking skills. Students with this experience are better equipped to make informed judgments about technical matters and to communicate and work in teams to solve complex problems. However, it is difficult to provide a quality experience to large numbers of students, particularly to students of differing abilities.The Systems and Software Engineering Affinity Research Group model provides a socialization mechanism and infrastructure that supports the development and management of large research groups that engage undergraduate and graduate students, who have a wide range of skill levels and experiences, in research and projects. This non-hierarchical model integrates students into both small research groups and an encompassing large research group, and uses structured activities to develop their research, technical, communication, and group skills.In this paper we introduce the model and report how the model meets independently developed Best Practice guidelines for student research experiences and we provide indicators of success for use by other projects.

The POEMS project is creating an environment for end-to-end performance modeling of complex parallel and distributed systems, spanning the domains of application software, runtime and operating system software, and hardware architecture. Toward this end, the POEMS framework supports composition of component models from these different domains into an end-to-end system model. This composition can be specified using a generalized graph model of a parallel system, together with interface specifications that carry information about component behaviors and evaluation methods. The POEMS Specification Language compiler will generate an end-to-end system model automatically from such a specification. The components of the target system may be modeled using different modeling paradigms and at various levels of detail. Therefore, evaluation of a POEMS end-to-end system model may require a variety of evaluation tools including specialized equation solvers, queuing network solvers, and discrete event simulators. A single application representation based on static and dynamic task graphs serves as a common workload representation for all these modeling approaches. Sophisticated parallelizing compiler techniques allow this representation to be generated automatically for a given parallel program. POEMS includes a library of predefined analytical and simulation component models of the different domains and a knowledge base that describes performance properties of widely used algorithms. The paper provides an overview of the POEMS methodology and illustrates several of its key components. The modeling capabilities are demonstrated by predicting the performance of alternative configurations of Sweep3D, a benchmark for evaluating wavefront application technologies and high-performance, parallel architectures.

Widely-used benchmarks are commonly classified as either scientific or commercial. Although process execution characteristics have been used as indicators of a benchmark's classification, a set of these characteristics along with a mechanism that can be used to easily compare and contrast workloads and partition them into classes with respect to these characteristics has not been identified. This paper identifies a set of process execution characteristics (PEC) that can be used to compare and contrast workloads and a method that can be used to partition workloads with respect to their PEC. These PEC, such as instruction locality, execution cycles per instruction, and context-switch frequency, are displayed with a high-density visualization tool called the PEC-Graph. Using the centroid linkage algorithm, processes' PEC are partitioned into clusters that are used to construct a taxonomy of workloads that is finer grained than taxonomies previously reported in the literature. The finer-grained categorization of workloads enables computer architects to select workloads that are known to stress specific architectural features, yielding potentially better performance analysis of new designs.

Dynamic Monitoring with Integrity Constraints (DynaMICs) is a software-fault monitoring approach in which the constraints are maintained separately from the program. Since the constraints are not entwined in the code, the approach facilitates the maintenance of the application and constraint code. Through code analysis during compilation, the points at which constraint checking should occur are determined. DynaMICs minimizes performance degradation, addressing a problem that has limited the use of runtime software-fault monitoring. This paper presents the preliminary design of a DynaMICs snoopy-coprocessor system, i.e., one that employs a coprocessor that utilizes bus-monitoring hardware to facilitate the concurrent execution of the application and constraint-checking code. In this approach, the coprocessor executes the constraint-checking code while the main processor executes the application code.

This paper discusses a particular network configuration plan used at New Mexico State University which enables us to effectively manage IP, Appletalk, and IPX. The network addressing scheme is based on an IP configuration of the network. From this configuration we derive Appletalk and IPX configurations. In this manner, we configure the network only once, and benefit from this configuration each time that we implement another network protocol. This configuration has helped us manage a network supporting 5000 hosts in 100 buildings at five geographically distinct locations. We believe that our network addressing scheme is simple and, hence, easy to administer. As we demonstrate in this paper, our scheme is easily applicable to other protocols and, therefore, can be a benefit to network managers.

We feel strongly that a contemporary introductory course in machine organization and assembly language should focus on the essentials of how computers execute programs, and not be distracted by the complications of the extraordinarily sophisticated microprocessors that are available today. These essentials should form a strong base of knowledge from which students can draw as they continue their education in computer science. Ideally these goals should be attained in an environment that fosters experimentation and cooperation, and with the aid of projects that generate interest and enthusiasm among the students. We have developed and are currently teaching a course at New Mexico State University that meets many of these goals. The course concentrates on a simple but relatively complete microprocessor architecture, that of the Motorola 68HC11 processor. Three different teaching techniques are used to encourage experimentation and team work: learning sessions, simulator labs, and microprocessor labs. New concepts are introduced in learning sessions, which combine traditional lecturing with student exploration. The understanding of these new concepts is strengthened through labs and assignments. Simulator labs and assignments, which require interaction with a simulator of the Motorola 68HC11 microprocessor, focus on the 68HC11's instruction set architecture. Microprocessor labs and assignments, which essentially are designing and building sessions, focus on the use of a 68HC11 microprocessor to control a motorized vehicle. During microprocessor labs students populate printed circuit cards, build motorized vehicles (or other roboticized exotica), and design and implement assembly language programs that provide communication between a personal computer and a 68HC11 processor, and a 68HC11 processor and a motorized vehicle. We have found that the costs of running this course are minimal and the results are very favorable in terms of student enthusiasm and achievement.

We present an updated report on the NYU Ultracomputer design emphasizing recent results on programming, operating systems, caching, demand paging, and I/O.The user's view of the Ultracomputer is presented along with the hardware and software implementation.Freedom from serial bottlenecks in both hardware and software allows the Ultracomputer to obtain performance that scales nearly linearly in the size of the machine for a broad spectrum of problems.