The heart of a massively parallel computer is its interconnection network. In this article we present a reconfigurable multiple bas network to support circuit switching as means of communication between processors of a multiprocessor machine. The main contribution of the papers is in demonstrating the simplicity of the routing hardware whilst still providing modularity and full utilization of the multiple bus system. A comparison with major interconnection network is also presented.

This study investigates the usefulness of wavelet transforms in phoneme recognition.Both discrete wavelet transforms (DWT) and sampled continuous wavelet transforms (SCWT) are tested.The wavelet transform is used as a part of the front-end processor which extracts feature vectors for a speakerindependent HMM-based phoneme recognizer.The results are evaluated on a portion of TIMIT corpus consisting of 30293 phoneme tokens for training and 14489 phoneme tokens for testing.The test results suggest that SCWT gives considerably better recognition rate than DWT.On the other hand, the improvement of SCWT over Mel-scale cepstral coecients appears to be marginal.

The Discrete Wavelet Transform (DWT) is a signal processing technique popularised by its results in data compression. Considerable work has been done in designing novel architectures to perform the DWT, including a systolic architecture designed by the authors, but little attention has been given to the inverse DWT which is needed in applications such as data compression for signal reconstruction. Despite the fact that the inverse DWT is computationally the reverse of the DWT, the hardware design for the architecture is not simply mirrored. Existing designs expect the architecture for the inverse DWT to be a simple follow-on step from the DWT design, however this is not the case. We present one such problem here, showing the FIFO buffering required on the input of the inverse architecture. We show how the size of this buffer can be calculated and compare it to a fixed data array implementation. This work is based on our systolic array design and is an integral part of the inverse DWT design we are working on for image and video compression.

Article Free Access Share on PIPADS—a low cost real-time visualization tool Authors: A. Spray Department of Electrical and Computer Engineering, The University of Newcastle, NSW 2308, Australia Department of Electrical and Computer Engineering, The University of Newcastle, NSW 2308, AustraliaView Profile , H. Schröder Department of Electrical and Computer Engineering, The University of Newcastle, NSW 2308, Australia Department of Electrical and Computer Engineering, The University of Newcastle, NSW 2308, AustraliaView Profile , K. T. Lie Department of Electrical and Computer Engineering, The University of Newcastle, NSW 2308, Australia Department of Electrical and Computer Engineering, The University of Newcastle, NSW 2308, AustraliaView Profile , E. Plesner Department of Electrical and Computer Engineering, The University of Newcastle, NSW 2308, Australia Department of Electrical and Computer Engineering, The University of Newcastle, NSW 2308, AustraliaView Profile , P. Bray Department of Electrical and Computer Engineering, The University of Newcastle, NSW 2308, Australia Department of Electrical and Computer Engineering, The University of Newcastle, NSW 2308, AustraliaView Profile Authors Info & Claims Supercomputing '93: Proceedings of the 1993 ACM/IEEE conference on SupercomputingDecember 1993 Pages 398–407https://doi.org/10.1145/169627.169761Published:01 December 1993Publication History 1citation210DownloadsMetricsTotal Citations1Total Downloads210Last 12 Months9Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

A method for maintaining causality within medium grained cellular based architectures is discussed. The strategy combines the benefits of data-driven communication with a hardware simplicity, latency and throughput rate approaching that of globally checked systolic arrays. It is shown that with this strategy higher throughput rates and lower latencies can be achieved by using slower processing elements.>