An analytical study of a multi-stage switched-capacitor (SC) voltage boost converter (VBC) for ultra-low voltage energy harvesting is presented. Because the output impedance of the VBC plays an important role in the VBC's performance, we developed an analytical model to achieve a highly efficient VBC. In our proposed method, we focus on currents flowing into input and output terminals of each stage and model the VBCs using switching frequency f, charge transfer capacitance Cf, and load capacitance CL. A comparison between simulated and calculated results showed that our model can estimate the output impedance of the VBC accurately. Our model is useful to compare the relative merits of different types of multi-stage SC VBCs.

This paper proposes an ultra-low power active diode using a hysteresis common gate comparator for low-voltage and low-power energy harvesting systems. The proposed active diode consists of a MOS switch and hysteresis common gate comparator, which eliminates unwanted ripple and noise voltages. The hysteresis comparator controls the MOS switch to turn ON or OFF, depending on the input and output voltages. The hysteresis voltages of the comparator can be controlled by the current flowing in the comparator. Simulation results demonstrated that the hysteresis comparator has a -27 and 25 mV hysteresis voltages and the active diode using the hysteresis comparator eliminates unwanted ripple voltage.

We propose a sub-1-μs start-up time, fully integrated 32-MHz relaxation oscillator (ROSC) for intermittent VLSI systems. Our proposed ROSC employs current mode architecture that is different from conventional voltage mode architecture. This enables compact and fast switching speed to be achieved. The measurement results demonstrated that the ROSC achieved sub-1-μs start-up time and generated stable output frequency of 32.6 MHz. Measured line regulation, temperature coefficient, and variation coefficient in 10 samples were ±0.69, ±0.38, and 0.62%, respectively.

In this paper, we propose a fully integrated and area-efficient resistor-less relaxation oscillator (ROSC) for ultra-low power real-time clock (RTC) applications. The proposed ROSC is based on a conventional ROSC and modified to be area-efficient circuit configuration, without using resistors. The proposed ROSC consists of a bias current source, proportional to absolute temperature (PTAT) voltage source, current mode ROSC, shunt regulator, and output logic circuit. The PTAT voltage source and shut regulator are used to compensate for the temperature characteristics of the ROSC. By implementing our proposed ROSC in a 65-nm CMOS process, the area was 0.022 mm2. Simulated results demonstrated that our proposed ROSC generates 32.5-kHz clock frequency and achieves ultra-low power dissipation of 271 nW. The temperature and voltage dependences of the oscillation frequency were 138ppm/°C and 13.9ppm/mV, respectively. Monte Carlo statistical simulations showed that the mean, standard deviation, and the coefficient of variation are 32.3 kHz, 0.6 kHz, and 1.9%, respectively.

We propose a fully integrated 3-terminal voltage converter with a maximum power point tracking (MPPT) circuit for ultra-low voltage energy harvesting. The MPPT circuit dissipates nano-watt power to extract maximum output power. The measurement results demonstrated that the circuit converted a 0.49-V input to a 1.46-V output with 73.6% power conversion efficiency when the output power was 348 μW. The circuit can operate at an extremely low input voltage of 0.21 V.

In this paper, we propose a low-power level shifter (LS) capable of converting extremely low-input voltage into high-output voltage. The proposed LS consists of a pre-amplifier with a logic error correction circuit and an output latch stage. The pre-amplifier generates complementary amplified signals, and the latch stage converts them into full-swing output signals. Simulated results demonstrated that the proposed LS in a 0.18-μm CMOS process can convert a 0.19-V input into 1.8-V output correctly. The energy and the delay time of the proposed LS were 0.24 pJ and 21.4 ns when the low supply voltage, high supply voltage, and the input pulse frequency, were 0.4, 1.8 V, and 100 kHz, respectively.

A low-power current reference circuit was developed in a 0.35-μm standard CMOS process. The proposed circuit utilizes an offset-voltage generation subcircuit consisting of sub-threshold MOS resistor ladder and generates temperature compensated reference current. Experimental results demonstrated that the proposed circuit generated a 95-nA reference current, and that the total power dissipation was 586 nW. The temperature coefficient of the reference current can be kept small within 523ppm/°C in a temperature range from -20 to 100°C.

We propose the use of a super-resolution (SR) technique for thermographies. This system captures several thermal images for a reconstruction-based SR. However, it does not require the subpixel registration required by conventional SRs. In this system, a pair of a low-resolution thermal image and a high-resolution visible image is captured synchronously. While the thermal images are used as source data for SR, the visible images are used for pixel registrations. Because the resolution of the visible images from CCD sensors is over 4 times higher than that of the thermal images, a simple pixel registration on the former is equivalent to a precise subpixel registration on the latter. Thus, we can reconstruct a high quality thermogram, without the need for a complex subpixel registration technique. Experimental results demonstrate that a pair of a thermographic camera with only 8×8 pixels and a visible CCD camera with 320 × 240 pixels generates a thermogram with 32 × 32 pixels. This fact means that a pair of a low cost thermographic camera and a standard CCD camera provides high-quality thermography.

A novel approach for data transmission in N-ISDN (narrow band integrated services digital network) is proposed. This approach uses the ATM (asynchronous transfer mode) technology normally applied to B-ISDN (broad band ISDN) and provides high performance for the simultaneous transmission of several types of burst information using a single N-ISDN line. It will be compatible to B-ISDN in the future. In the paper, the proposed transmission model is first outlined, including its system description, the layer construction and the functional elements. Then, the transmission protocol is described in detail. Finally, a simulation system is realized, and the performance of the transmission system is confirmed by the simulation results which show the usefulness of the proposed data transmission mode.>