Hexapods are widely used for precision positioning, but their workspace is too limited for some applications. Often, a rotary stage is added to enlarge the orientation workspace, but this increases the system cost. As an alternative, rotary hexapods have been proposed in which the legs are of fixed length and the base attachment points slide along a common circular path. However, these hexapods have a reduced range of motion in some degrees of freedom due to mechanical interferences. In contrast, we propose a design in which two concentric circular rails are used in addition to double spherical joints, three extra rotary sensors, and two high-accuracy rotary encoders. As a result, the workspace of our robot is significantly increased, its direct kinematics can be solved linearly, and its high accuracy is guaranteed. A prototype has been built and is described in detail.

A method for enhancing the noise-power tradeoff of front-end amplifiers in parallel recording applications is proposed. The circuit uses shared-input transconductance amplifiers and differential readout to attenuate correlated noise between parallel outputs, resulting in significant supply current savings without noise penalty. Also, a method for reducing the remaining noise with little power penalty is proposed. The potential benefits of combining both methods and the related trade-offs are discussed and validated by simulations on a sample design intended for ENG recordings, using models of a 0.35μm BiCMOS process. It is shown that the total supply current can be reduced by more than 50% that of a comparable system using conventional differential amplifiers with equivalent output noise. Alternatively, the noise can be reduced by approximately 35% with comparable power consumption.

We present in this paper a current mediated active pixel sensor (APS) with variable image size and resolution for power saving, electronic zooming, and data reduction at the sensor level. The circuit can perform averaging of output signals in blocks of adjacent pixels (kernels) of size 1/spl times/1, 2/spl times/2 and 4/spl times/4, allowing data reduction without aliasing effects. To achieve this, a current approach is used, thus enabling high speed operation and low power supply capacity. A novel fixed pattern noise (FPN) reduction scheme using a compact circuitry is presented. The circuit compensates for pixel transconductance mismatch in addition to offset error via analog to digital conversion reference current scaling. Hspice simulations using parameters of a 0.35 /spl mu/m CMOS process illustrate the advantage of the new technique over usual correlated double sampling (CDS) in current mode sensors. Parallel integrated analog to digital converters (ADC), a data line-buffer and digital control complete the circuit making data transmission easy and simplifying hardware needed for using the image sensor.