This paper presents a voltage reference design that combines a BJT-based voltage reference with a weak inversion current correction technique to reduce the TlnT nonlinearity inherent in most BJT-based reference. The proposed design combines the temperature characteristics of both BJTs and subthreshold MOSFETs to eliminate both the T and the TlnT effects in the output of the voltage reference. Simulation results show that the proposed voltage reference will exhibit a sub 1ppm/℃ temperature coefficient over the temperature range from -40℃ to 125℃. The power supply ripple rejection is -70dB while operating between 1.5V and 2V in a standard 180nm bulk CMOS process. The design delivers low line-regulation of 0.028%.

A compact CMOS temperature sensor suitable for on-chip power/thermal management designed to monitor hotspot formation at multiple locations on a die is introduced. Temperature information is embedded in the ratio of two voltage outputs of the sensor to facilitate temperature to digital conversion without the need for a separate reference for the data converter. The sensor is highly insensitive to temperature or stress-dependent bias current variations. Measured results in a sensor with devices from a 0.5μm CMOS process show an error of ±0.5°C over the temperature range of -10°C to 100°C when biased with a constant current. Even with ±5% variation in bias current an error of less than ±1°C over the -10°C to 100°C temperature range is achieved.

This paper presents a resistorless curvature-compensated bandgap voltage reference (BGR). The proposed method, using ratioed transistors and the inverse function technique, attempts to extract VGO, the bandgap voltage of silicon, by canceling out both the T and TlnT terms in the temperature characteristic of the bipolar junction transistor's (BJT) base-emitter voltage, VBE. The proposed design is implemented in the TSMC 180nm process. Simulation results show that the circuit can achieve temperature coefficients (TC) of less than 4.7ppm/°C from −20°C to 80°C over process variation and mismatch.

A strategy for designing a high accuracy voltage reference operating at sub 1ppm/°C over a wide temperature range is introduced. The proposed design makes use of one of the popular and widely used bandgap voltage reference structures and the temperature dependence of the drain current of a single MOS transistor operating in subthreshold to build a sub-ppm/°C voltage reference. The effects of error sources which may affect the performance of the voltage reference are analyzed and minimized. Simulation results in the TSMC 180nm process show that the design can achieve temperature coefficients of less than 0.85ppm/°C across process corners and local random variations from −40°C to 125°C after trimming.

Hardware security vulnerabilities to hardware Trojans in widely used filter structures are identified. The widely used two-integrator loop filter architecture known as the Kerwin-Huelsman-Newcomb (KHN) Biquad is used to demonstrate the vulnerability. It is shown that the relationship between the passive component values and the nonlinear amplifier parameters, the slew rate and the output saturation voltages, determine the presence or absence of a stationary nonlinear undesired oscillatory mode of operation. Experimental results obtained from a discrete component filter demonstrate the vulnerability to the Trojan mode of operation in this filter structure.

A general approach based on a natural basis function expansion to cancel the temperature-curvature of the base-emitter voltage in the bipolar transistors embedded in bandgap references is presented. The proposed method can be applied to the widely used Banba, Kuijk, and Brokaw structures to build references with sub-ppm/°C temperature coefficients. Current version and voltage version embodiments based on a self-bootstrapping concept are provided. Error sources that can potentially affect the reference performance are analyzed and their effects on the temperature coefficient are minimized after trimming. Monte Carlo simulation results confirm that after calibration, temperature drift performance is within the design/trimming target 0.5 ppm/°C. A partially integrated Kuijk-based prototype reference has been designed and fabricated in a 65nm UMC process. Measurement results demonstrated a 1.5 ppm/°C temperature coefficient over a temperature range of 0 °C to 80 °C with a low-cost two-temperature trimming method. With additional trimming, 0.8 ppm/°C performance was achieved.

This paper presents a general approach to extract VGOfrom the base emitter voltage of a bipolar transistor. VGOis the silicon bandgap voltage at zero Kelvin and it is a physical constant voltage independent of temperature. The proposed method can be implemented on any of the widely used Banba, Kuijk, Brokaw or resistorless structures to build voltage references with sub-ppm/°C temperature coefficient. One embodiment based on Kuijk structure is used to illustrate how the proposed VGOextraction can be realized. Error sources which can affect the voltage reference's performance are analyzed with a new base expansion and their effects on the temperature coefficient are minimized after the proposed two-temperature trimming. Transistor level simulations are run in GlobalFoundries 130nm process and simulation results show that the design can achieve 0.5 ppm/°C temperature coefficient from -40 °C to 125 °C.

Built-in self-test(BIST) for AMS circuit is widely investigated and developed in the last decade since it is a promising alternative to traditional testing. In particular, SEIR (stimulus error identification and removal) based BIST circuit has been proved to be a cost effective and practical ADC BIST solution for ADC testing. The SEIR method can relax the linearity requirement of input signal for ADC. However, high constancy of level shift between two signals are needed for testing high resolution ADC's linearity. This paper presents a new method to introduce the highly constant level shift and a new structure of output buffer with true rail-to-rail performance without degrading close-loop gain by applying correlated level shifting (CLS)technique. The simulation results show that the constancy of level shift is only 2.2ppm over the entire ADC input range. The constancy level is able to test 18 bit ADC to 18 bit accuracy level for full-codes testing.

A transparent side channel trigger mechanism triggering Power/Area/Architecture and Signature Transparent (PAAST) analog hardware Trojans is discussed in this paper. By applying this trigger mechanism through normal supply bus, the circuit can be triggered to the Trojan state. Same as the stealth nature of PAAST Trojans, it doesn't require any additional area, any additional power, any structure modifications and it doesn't leave any signatures in either power domains or signal paths. This trigger mechanism can be applied on circuits with static Trojans or circuits with dynamic Trojans.

This paper presents a complete on-chip ADC BIST solution based on a segmented stimulus error identification algorithm known as USER-SMILE. By adapting the algorithm for efficient hardware realization, the solution is implemented towards a 1Msps 12-bit SAR ADC on a 28nm CMOS automotive microcontroller. While sufficient test accuracy is demonstrated, the solution is further extended to correct linearity errors of ADC. The entire BIST and calibration circuitry occupies 0.028mm2silicon area while enabling more than 10 times tester time reduction and >10dB THD/SFDR performance improvement over an existing structural capacitor-weight-identification calibration scheme. The added die cost is estimated to be 1/8 of the saved test cost from tester time reduction alone.

A programmable temperature trigger circuit with thermal hysteresis that is suitable for on-chip thermal management applications is proposed. The circuit utilizes a simple Schmitt Trigger structure. Both the location and the width of the hysteresis window are programmable. The temperature trigger circuit is designed in a 0.13um IBM CMOS process and operates with a supply voltage of 1.2V. Both the power dissipation and the silicon area are very small.

A temperature to digital converter (TDC) that does not require either a reference generator or an ADC and that exhibits low supply sensitivity, small die area, and low power consumption is introduced. A prototype circuit designed to support power management applications over the [60 °C, 90 °C] temperature range was implemented in an IBM 0.13μm CMOS process with a 1.2V power supply for use as either a temperature trigger or a digital thermometer. Simulation results show the maximum temperature error over this range is less than ±0.5°C. The total silicon area for the TDC is only .004mm2.

A calibration technique for SAR analog-to-digital converters is proposed in this paper which is ready to be integrated on chip. This technique is based on the integral nonlinearity (INL) test and utilizes one redundant bit and extra two quantization bits to improve the calibration accuracy. In the calibration mode, mismatch errors are saved as higher-bit level INL information and then translated to calibration codes. During the conversion, higher-bit level outputs are adjusted and truncated to generate the required bits. Finally, 0.375LSB improvement of INL is observed by theoretical analysis and the effectiveness of this method is verified by simulations in which the maximum INL is reduced from 0.9LSB to 0.23LSB.

A systematic method is proposed for automatically identifying and breaking positive feedback loops (PFLs) in Trojan States Vulnerable Circuit. The method first converts the netlist of a circuit into a directed dependency graph (DDG) and then partitions the DDG into strongly connected components (SCCs). It then employs graph theory techniques to detect all PFLs and locate the break-points for every SCC. The proposed method could identify the circuit's vulnerability to Trojan States only by its structure without the computation of DC solutions and it also provides insights on how and where to break the PFLs such that break-loop continuation methods can be applied. With Sub-Bandgap reference and widlar-Banba examples, it is demonstrated that the proposed approach can effectively identify all the PFLs and break-points.

A systematic method is proposed for automatically identifying positive feedback loops (PFLs) in analog/mixed-signal circuits. The method first converts the netlist of a circuit into a directed dependency graph (DDG) which captures the critical relationships among branch currents and node voltages. It then utilizes graph theory techniques to find all feedback loops from the DDG and finally, criterion are developed to determine the PFLs. Since multiple states is caused by the PFLs, this method could identify the circuit's vulnerability to undesigned operating points only by its structure without the computation of DC solutions. The proposed approach is implemented in program and simulation results show it could identify all the PFLs very robustly.

An empirical reliability model for electromigration-induced failure in metal interconnects under thermal, electrical, and thermal gradient stress is introduced. Based upon the limited reported measurements on static thermal gradient stress that are available, this model incorporates thermal gradient stress into the probability density function of the time to failure, tF. With this model, temperature measurement accuracy and temperature gradient measurement accuracy requirements for multi-site on-chip sensors that can be used in power/thermal management algorithms are developed that target achieving 10% accuracy in the median time to failure (MTF) of a circuit.

Spectral testing is important to measure the frequency characteristics of an Analog to Digital Converter. It is an expensive and challenging task to perform coherent sampling and to acquire highly pure signal generators for spectral testing. For the first time, a method that can eliminate the requirements of both coherent sampling and highly pure signal generators to perform accurate spectral test is proposed. Simulation results show the ability of the proposed method to accurately test a 15-bit ADC using a non-coherently sampled input signal with SFDR of 39dB. Furthermore, the robustness of the proposed method over the whole range of non-coherency is presented. The method can be applicable for ADC production test.

Several methods that can be used to verify effectiveness of startup circuits in eliminating known stable Trojan operating states will be discussed. It will be shown that some widely used approaches do not guarantee Trojan states have been removed. Some of the methods introduced appear to be more practical to work with than others. These methods can also be used to identify the presence of unknown stable Trojan states in many useful circuits.

An accurate, small, low-power CMOS temperature sensor for on-chip thermal monitoring is proposed. The temperature sensor utilizes the temperature characteristics of the threshold voltage of a MOS transistor to sense temperature and is quite linear over the in temperature range (-20C, 100°C). The threshold-based temperature sensors were designed in the ON Semiconductor 1P6M (Single Poly, 6 Metal) 180nm process with a 1.8V supply voltage. The die area of this circuit is only 14.8μm×22.2μm. It has low power consumption of about 1.026μW at a 1% duty cycle. Measurement results show that a batch of 5 temperature sensors have a nonlinear error bounded of -0.21°C to +0.17°C with a one-point calibration and batch slope/curvature correction over the target operating temperature range (-20°C, 100°C).

As the Systems-on-Chips (SoCs) complexity increases, test cost contributes more in the total cost. Especially, test of deeply embedded analog and mixed signal blocks are the most costly test. Built-In Self-Test (BIST) is considered as a low cost substitution of traditional production test. This paper presents a low cost method for testing ADC's offset and gain error. This is a complement of previous published linearity and spectral performance test methods. The simulation results show the method has good accuracy.

A novel technique to generate spectrally pure sinusoidal signals is proposed. The technique provides a dramatic improvement in spectral performance compared to the existing state of the art. With the proposed approach, spectral performance is inherently robust to variation in operating frequency and spectral characterization is programmable over frequencies. A circuit using extremely low cost operational amplifiers and 5 % accurate passive components has been built that can generate a sine wave with THD of lesser than -100dB at frequency, f=2.737 KHz .

A simple low-power current reference using dual-threshold MOS transistors is introduced. The area required for this reference is small and the sensitivity of the output current to the supply voltage is low. Simulation results show that an implementation of this current reference in a TSMC 0.18um CMOS process with a 1.8V power supply is constant to within ±1.25% over the temperature range of -10°C to 100°C. In this implementation, the active area is 86 μm2, the power dissipation is 72μW, and the worst process corner nonlinearity due to temperature variations is bounded by ±4.16%.

A new on-die temperature sensor that operates at low supply voltages and exhibits low process sensitivity and good linearity over a wide temperature range is introduced. When compared to conventional structures which have limited supply voltage headroom at the slow-n process corner, the new structures have sufficient headroom to practically operate well over all process corners. When implemented in a TSMC 0.1 Sum process with a nominal supply voltage of 1.8V, simulation results show the maximum temperature linearity error is reduced from 1.5°C to less than 0.3°C at the NMOS slow process corner and with negative 10% Vdd variation.

Coherent sampling is required in ADC testing. Unlike production testing in which fractional frequency is available, only sampling clock of ADC is available for ADC Built-in Self-test (BIST). Triangular stimulus generator controlled by sampling clock of ADC cannot provide enough information because same voltages are sampled in every period. To carry out valid data acquisition, different voltages in different period should be sampled. Instead of generating fractional frequency, a method of introducing delay to every ramp in triangular wave is proposed in this paper. An 8-bit digital to time converter (DTC) is designed to provide needed number of delays. A control scheme is proposed to provide both phase control of triangular stimulus and testing control of BIST. Simulation results show control scheme works well for linearity test and delayed triangular wave provides valid data acquisition for histogram test. Errors in delay affect test results very little.

Due to the positive feedback and the time varying clock signal, the operating point of each transistor in dynamic comparators is time varying and cannot be analyzed using traditional Op-Amp-based small signal analysis. Until recently, a balanced method is proposed to effectively get the analytical models for random offset caused by variations in process parameters. Meanwhile, it has been shown that mismatches from parasitic capacitors are also significant contributors to overall offset. However, the energy storage and nonlinear feature of capacitor make it even more challenging to analytically predict the capacitive mismatch induced offset. In this work, the previous proposed balance method is generalized and applied to tackle the problem of capacitive mismatch induced offset. The analytical models are derived to explicitly show offsets caused by capacitor mismatch at different internal nodes. The insights are obtained on identifying the sensitive nodes to capacitor mismatch and on how to reduce the offset. The numerical example validates the effectiveness of the analytical models.

Traditional linearity testing of ADCs involves using a spectrally pure or a highly linear stimulus, along with a large number of samples per code to average out the effects of noise. Test equipments need to house expensive instruments to provide the highly linear stimulus. The large number of samples required for the procedure results in long test times. These two factors are prime contributors to the test cost. In this paper, algorithms which use low linearity stimuli and a Kalman Filter to reduce both the hardware resources and the test time for the test procedure have been proposed. Simulations results for a 14-bit ADC show that a 7-bit linear stimulus with one sample per code can be used to measure the INL of the ADC with a maximum estimation error of 1 LSB.

ADC in SOC usually has no connection to the outside. Built-in self-test is a good way to verify this block's performance. Stringent requirement of stimulus generator is the most important limitation of ADC BIST. Several methods of using stimulus with low linearity to test ADC with high linearity have been reported for standalone production test. These methods can be adapted for ADC BIST to reduce the BIST cost overhead. This paper investigates signal patterns that can be used in low cost BIST scheme. Two cost effective stimulus generator structures are presented. Simulation results shows that the generated signal with less than 7 bits linearity can be used to test a 16 bits ADC. The estimation errors of INL are less than 0.65 LSB.

The relationship between yield, area, and impedance distribution in dual-string DACs is developed. Optimal area allocation and impedance distributions strategies for maximizing yield in the presence of local random process variations are introduced. Simulation results show that a factor of 4 or more reduction in area for a given yield is possible if typical area/impedance allocations are replaced with an optimal area/impedance allocation.

In a dynamic comparator, it's always challenging to analytically predict the input offset voltage due to the existence of the internal positive feedback and transient process. In this paper, a simple method is presented to accurately estimate input offset voltages caused by process variations in dynamic comparators. The "Lewis-Gray" comparator implemented in TSMC0.25mum process is applied as an example to verify the effectiveness of the analytical method. Based on the SPICE level 1 model, the method shows good agreements with Monte Carlo transient simulation based on the sophisticated BSEVI3V3 model. The analytical results allow the circuit designers to fully explore the tradeoffs in comparator design, such as offset voltage, area and speed. To illustrate the potential, the analytical method was used to re-size the "Lewis-Gray" structure to reduce its random offset while maintaining a constant total area. After the optimization, input offset voltage has been reduced by 41% compared with its original sizing.

Adjustable hysteresis CMOS Schmitt trigger design strategies are investigated and two new inverter based designs are proposed. The sizing of the two feedback inverters controls the two trip points of the structure independently. By the addition of voltage controlled current sinking and/or sourcing transistors, the hysteresis window can be easily moved without changing its width. Moreover the new designs are immune to the kick-back noise coming from the succeeding blocks.

This work presents a system identification-based reduced-code testing method for pipeline ADC’s linearity test. In the method, the pipeline ADC under test is identified by characterizing the two most critical parameters in each stage, the stage gain and the comparator offset. The transfer function is investigated to obtain the effects of the gain error and comparator offset on ADC’s linearity performance. With the measurements of a small set of specific transition levels or code bin widths, the system parameters of interest can be achieved using only straightforward linear calculations. The identified model is then used to compute the ADC’s full-code linearity performance. Comparing to standard histogram-based full-code linearity test methods, the proposed method can reduce the data capture time by a factor of several hundreds without appreciably degrading the testing accuracy. Both simulation results and experimental results are included to demonstrate the efficacy of the proposed method.

This paper presents the study of a well established linear current division circuit, which has been referenced many times in published works as a basic building block in variety applications up to date. Understanding the advantages and, even more important, the limitations of this technique would benefit the further exploiting of potential applications. Analytic study with close form expressions shows highly agreements with the original statement that this structure is inherently linear and the linearity is independent of the electrical variables and only relies on the transistors geometrical match performance. However, the more accurate study with simulation results suggests that there are limitations for using this technique in terms of high linearity in the most popular semiconductor processes. Thereby more general circuit principles behind reported high linearity is of particular interested.

A rigorous and complete analysis of the deterministic DEM (DDEM) DAC performance is presented. With this analysis, DDEM DAC's equivalent linearity as ADC static linearity test stimulus source can be precisely predicted. Simulation result is given to validate this theoretical analysis.

Digital testing is much easier and cheaper than analog and mixed-signal testing because of the straightforward connections and the low-cost testers. This paper presents a fully digital-compatible built-in self-test strategy for ADC linearity testing using all digital testing environments. Onchip, low-accuracy DACs, which are area efficient and simple to design, are implemented as the stimulus generator. ADCs’ nonlinearities are tested using a histogram-based method under the control of a logic block. The described strategy is capable of characterizing ADC transition levels one by one with small hardware overhead. Simulation and experimental results show that the proposed circuitry and BIST strategy can test the INLkerror of 12-bit ADCs to ±0.2LSB accuracy level using only 7-bit linear DACs.

High-precision ADC testing is a challenging problem because of its stringent requirement on test signal's linearity. This work introduces a method using a nonlinear stimulus signal for testing linearity of high-resolution cyclic and pipelined ADCs by exploiting their architecture information. Simulation and experiments show that 16-bit ADCs can be tested to 1-LSB accuracy by using a 7-bit linear signal. This approach provides a solution to both the production and on-chip testing problems of high-resolution ADCs.

Conspicuously absent in the literature are explicit relationships between the output voltage and temperature of bandgap references. In this paper an explicit relationship for the output voltage of a popular bandgap reference structure is developed. Within the context of this explicit relationship, temperature stability properties of references are explored

This work introduces a multi-segment bandgap reference circuit with self-calibration. Thermal characteristics of the bandgap circuit were modeled using test results under normal temperatures. With the characterization information, appropriate circuit parameters were calculated for different temperature intervals and used to adjust the inflection point of the bandgap curve as the temperature changes, in order for the reference circuit to achieve high thermal stability. Simulation results show that the proposed circuit can achieve a better than 0.5 ppm//spl deg/C temperature coefficient over a range of 140/spl deg/C. This circuit is compatible with most of the existing bandgap circuit structures and can be used in low-voltage designs.

Unit resistors are widely used in matching-critical applications. In good designs, matching performance is dominantly determined by the characteristics of the unit resistor. In this paper, a strategy for statistically characterizing the performance of unit resistors that combines the effects of contact resistance, contact size variations, sheet resistance and edge variations is introduced.

High accuracy digital to analog converters (DACs) are becoming increasingly important as the common used building block in communication systems. With the increasing of the update rate, dynamic performance of such DACs at high frequencies is of particular interest. The dynamic performance is often characterized by the spurious free dynamic range (SFDR) and the SFDR is limited by the spectral harmonics which are attributed by system nonlinearities. In this paper, the dynamic nonlinearity is analyzed and its effect on the output waveform is discussed. An approach is presented to calibrate the dynamic errors. The validity of this approach is demonstrated with a 15-bit current steering DAC. Simulation results show that the approach is robust and the SFDR can be correspondingly significantly improved by using this calibration scheme.

A useful theorem for the design of integrated active RC filters with minimum passive area is introduced and proven. A necessary condition for a minimum-area design is presented. Design examples based on the established condition are discussed.

This work proposed a built-in self-test (BIST) strategy for DAC linearity test by utilizing the deterministic dynamic element matching (DDEM) technique in a common flash ADC. DDEM technique allows low-resolution and low-accuracy ADCs work as test devices. In order to provide high resolution/accuracy test abilities, a fine quantization stage and an input dithering DAC are incorporated. In this paper, the architecture of the test system and the test procedure are described. The test performance is analyzed theoretically and verified by numerical simulation. Simulation results show that a two-step flash ADC composed of a 6-bit coarse DDEM stage and a 6-bit fine stage, plus an incorporated 5-bit dithering DAC, with linearity of all the blocks no more than 6 bits, is capable of testing 14-bit DACs.

In this paper, the well-known equation, which explicitly shows the temperature behavior of the I/sub C/-V/sub BE/ characteristics of the transistor, is applied to analyze a specific bandgap reference circuit. The theoretical analysis clearly characterizes some important features of the circuit, such as the value of the bandgap output, the relationship of the inflection point and the circuit parameters, the curvature of the bandgap curve and so on. Spectre simulations show a good consistency of the analysis. Based on the analysis, a new approach for designing high-precision references is also proposed.

This work introduces an efficient code-density linearity testing algorithm for ADCs that can achieve high accuracy within short test time. The proposed algorithm uses Kalman filtering to suppress the effect of errors in the histogram counts based on characteristics of input noise and circuit mismatches. Appropriate versions of the algorithm for ADCs of flash and pipelined architectures are introduced respectively. Simulation results show that this approach can reduce the INLkestimation error by over 50% and achieve desired accuracy with a much smaller number of samples as compared to the conventional algorithm. Simulation and experimental results show that the proposed algorithm can significantly shorten the linearity test time by a factor of 10 or higher. Therefore, it can enable test and help maintain the quality of high-performance ADCs, and reduce the production test time and cost for medium and low resolution ADCs

The bottleneck of DAC testing is the fast and accurate measurement devices. Production testing of high-resolution DACs with gigahertz clock rates is a challenging problem, and there is no widely adopted approach for on-chip testing of precision DACs in an SoC system. This work presents a new approach for testing high-resolution DACs. High speed data acquisition is achieved with flash ADCs; sufficient resolution is provided by dithering; and high test accuracy is guaranteed by the proposed data processing algorithm. This method provides a potential solution to both the production and on-chip DAC testing problems. Simulation results show that the static linearity of 14 bit DACs can be tested to better than 1 LSB accuracy, and dynamic performance of more than 85 dB SFDR can be tested with 1 dB accuracy, using 6-bit ADCs and dithering. Experimental results included in the paper also affirm the performance of the algorithm in testing high-resolution DACs using 6-bit ADCs

This work describes a linearity test strategy for ADCs that uses stimuli with precision much lower than the ADC resolution and tolerates environment nonstationarity. This approach can be applied to testing ADCs of very high performance, such as 16-bit or higher resolutions and more than 1 MSPS sampling rates, to which there is hardly a well-established solution for full-code test. Simulation and experimental results show that a 16-bit ADC can be tested to 1-LSB accuracy by using input signals of 7-bit linearity in an environment with more than 100 ppm per minute nonstationarity. The proposed method can also help control the cost of ADC production test, extend the test coverage and enable built-in self-test and test-based self-calibration.

A novel, on-chip transfer function calibration scheme is introduced to the classical resistor string DAC architecture. A 16-bit, quad channel, resistor string DAC with exceptional accuracy is fabricated on an ultra-low-cost, 0.5/spl mu/m, 5V CMOS process. Monotonicity is achieved by voltage interpolation and absolute accuracy errors are improved by 100/spl times/ using full transfer function calibration at final test. An on-chip arithmetic logic unit (ALU) linearly interpolates calibration coefficients saving memory, and a high-effective-resolution cal-DAC preserves differential linearity (DNL) performance while correcting integral linearity errors. Separate cal-DACs correct for offset and gain errors. Each DAC channel occupies 4mm/sup 2/ die area, consumes 750/spl mu/A, and settles in 10/spl mu/s, while offering up to +/- 500/spl mu/V absolute accuracy across its transfer curve. The chip has built-in DFT and uses one time programmable memory with read-back. The device can be calibrated and tested with a single insertion at final test. This paper discusses the architecture, testing, calibration and optimization details.

This work presents a deterministic dynamic element matching (DDEM) approach which is applied to low precision DACs to generate stimulus signals for ADC testing. Both simulation results and experimental results from a fabricated DDEM DAC are presented to verify the performance. The ADC testing performance of an 8-bit DDEM DAC (linearity less than 5 bits without DDEM) is comparable to or better than the best results reported in the literature using on-chip linear ramp generators. The DDEM technique offers great potential for use in both production test and built-in-self-test(BIST) environments.

The fast Fourier transform is the ubiquitous method of choice for spectral testing. However, its correct application to periodic signals requires either strict coherent sampling, or careful windowing, or other techniques that are computationally inefficient. This work introduces a new method for achieving accurate spectral testing for periodic signals without the need for coherent sampling or windowing. Furthermore the method is computationally very efficient with only minimal addition to the computational complexity of FFT. The method is validated with both simulation data and experimental data. Extensive controlled simulation indicates that the method is very robust to errors in signal frequency, phase, amplitude, additive noise, and so on. Statistical analysis and comparative studies demonstrate that the proposed method achieves spectral testing accuracies similar to those obtained with perfect coherent sampling in an ideal noise-free environment.

As the performance of Analog-to-Digital Converters continues to improve, it is becoming more challenging and costly to develop sufficiently fast and low-drift signal generators that are adequately more linear than the ADC for the purpose of linearity testing. This work relaxes the linearity requirements on the signal generators used for ADC testing by alternatively employing multiple non-linear inputs. Assuming minimal prior knowledge of the input non-linearity, a testing methodology is introduced that is based upon first identifying and computationally removing the source non-linearity and then accurately estimating the ADC linearity. Production test hardware is used for validating the performance of this testing methodology using a high performance 16-bit SAR ADC as a test vehicle. Integral linearity error readings are identified to well within the +/-2 LSB range of the device specification by using only 8-bit linear inputs. This approach provides an enabling technology for costeffective full-code testing of high performance ADCs in production test and for a cost-effective implementation of built-in self-test (BIST).

A new approach for testing mixed-signal circuits based upon using imprecise stimuli is introduced. Unlike most existing Built-In Self-Test (BIST) and production test approaches that require excitation signals that are at least 3 bits or more linear than the Device-Under-Test (DUT), the proposed approach can work with stimuli that are several bits less linear than the DUT. This dramatically reduces the requirements on stimulus generation for BIST applications and offers potential for using inexpensive signal generators in production test, or for testing DUTs that have a linearity performance exceeding that of the available test equipment. As a proof of concept, a histogram-based algorithm for linearity testing for Analog-to-Digital Converters (ADCs) has been proposed. It can estimate the Integral Nonlinearity (INL) and Differential Nonlinearity (DNL) of an n -bit ADC by using a ramp signal of much less than n -bit linearity and a shifted version of the same nonlinear ramp as excitation. The performance of the algorithm is comparable to that of the traditional method which uses ( n + 3)-bits or a decade more linear input signals. Complete algorithm description, extensive simulation results and experimental results obtained from using a production tester on commercially available ICs are presented to validate the potential of this algorithm.

A new current mirror structure using a non-rectangular dual-drain device with a shared channel to reduce the matching sensitivity to linear parameter gradients is introduced. The new structures are compared with conventional common centroid layouts for threshold voltage gradients at all angles across the active area of a mirror. Results show that in some applications, significant improvement in matching characteristics with the proposed non-rectangular structures over what is achievable with conventional layout techniques can be achieved.

A MOS active summing voltage attenuator along with the voltage attenuator proposed before by the authors form a set of attenuators particularly useful in analog monolithic applications. The performance of a finite gain amplifier employing the MOS active attenuator is discussed. Large signal and small signal multiple input monolithic finite gain summing and subtracting amplifiers employing the attenuators are presented.>

An accurate threshold voltage extraction scheme for MOS transistors is presented. The scheme differs from alternative methods recently reported in the literature in that it does not require matched replica of the transistor under test and thus can be applied more effectively and accurately to real-time on-chip applications where threshold voltage measurements are required for many transistors with various geometries and bias conditions. The proposed scheme is accurately implemented in a matching-free way using a ratio-independent switched-capacitor subtracting amplifier and a dynamic current mirror. Nonideal effects associated with these circuits are investigated.>